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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是151-160 订阅

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New 3D-integrated burst image sensor architectures with in-situ A/D conversion

New 3D-integrated burst image sensor architectures with in-s...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Bonnard, R. Guellec, F. Segura, J. Dupret, A. Uhring, W. DACLE-L3I CEA-Léti Grenoble France ICube/ESSP/SMH Université de Strasbourg CNRS Strasbourg France

ISBN: (纸本)9791092279016

It is well known that 3D integration technology brings a lot to image sensors in term of fill-factor and in-situ processing. As 3D stacking allows massively parallel processing, it looks like an effective way to store the image close to the pixel in burst image sensor. This paper discusses two new 3D stacked architectures for burst high speed imaging with in-situ A/D conversion, one with analog memories, the other based on digital storage. We propose appraisals of frame-rate, memory depth and power consumption for both architectures. Thanks to this assessment, analog storage architecture appears as a good way to reach unmatched speed performances (>10Terapixel/s) while digital storage architecture seems an interesting solution to reach high memory depth (>200 frames). Moreover, this study identifies a very high power consumption of the digital and analog storage architectures during the image capture.

关键词： image sensors

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A prototype of an adaptive computer vision algorithm on MPSoC architecture

A prototype of an adaptive computer vision algorithm on MPSo...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Sousa, Éricles Rodrigues Tanase, Alexandru Hannig, Frank Teich, Jürgen Hardware/Software Co-Design Department of Computer Science University of Erlangen-Nuremberg Germany

ISBN: (纸本)9791092279016

Continuous software and hardware innovations impose on the one hand a high degree of flexibility from an algorithm and on the other hand it requires that a given processing architecture has the capability to adapt to changing computation patterns at run-time. In this work, we demonstrate how a computer vision application can adapt itself at runtime in order to satisfy different requirements of quality and throughput. For that, we consider an implementation of the Harris Corner Detector on an MPSoC (Multi-Processor System-on-Chip) architecture composed of a quad-core RISC processor and one accelerator based on a programmable massively parallel processor array.

关键词： System-on-chip

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Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform

Memory access analysis and optimization of a parallel H.264/...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Brandenburg, Jens Stabernack, Benno Fraunhofer Institute for Telecommunications Image Processing Department Embedded Systems Group Einsteinufer 37 10587 Berlin Germany

ISBN: (纸本)9791092279016

HW/SW co-design and optimization requires an in-depth performance and bottleneck analysis of the developed system. Due to the increasing gap between the performance of the processing elements and the memory subsystem also memory access analysis plays an important role in this optimization task. This is especially the case for state of the art media signal processing applications, like video decoders, with their growing demand for high memory bandwidths and low latency data accesses. Optimizing memory partitioning, memory hierarchy, memory characteristics and allocation of data structures formulates a multidimensional HW/SW co-optimization problem with increasing complexity due to the trend towards embedded multi-core platforms. In order to aid the developer with these optimization tasks, performance and memory access analysis tools are needed. Nowadays there exist many different vendor specific debug and profiling tools for different processor architectures addressing different aspects of the overall co-optimization problem. Moving to heterogeneous platforms makes the combination and integration of the different profiling data a challenging task. Moreover it is important to combine the profiling results with information gathered from dedicated components, like interrupts, signals and/or synchronization events, representing the actual hardware platform. To overcome this issue we propose a flexible tracing and profiling methodology capable to trace all hardware aspects of the modeled simulation platform. Based on this methodology we developed a tool, which gives a comprehensive overview of the software tasks running on the various processing elements of the particular execution platform. Furthermore our tool provides detailed non-intrusive memory access and performance analyses based on SystemC virtual platform simulation models for heterogeneous embedded multi-core platforms. A demonstration of the tools capabilities is given by an exemplary analysis of a Scalable Vi

关键词： Video signal processing

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Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters

Architecture and programming model support for efficient het...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Burgio, Paolo Marongiu, Andrea Danilo, Robin Coussy, Philippe Benini, Luca LabSTICC Université de Bretagne-Sud Lorient France ERC MultiTherman Lab DIE Università Degli Studi di Bologna Italy

ISBN: (纸本)9791092279016

Modern computer vision and image processing embedded systems exploit hardware acceleration inside scalable parallel architectures, such as tightly-coupled clusters, to achieve stringent performance and energy efficiency targets. Architectural heterogeneity typically makes software development cumbersome, thus shared memory processor-to-accelerator communication is typically preferred to simplify code offloading to HW IPs for critical computational kernels. However, tightly coupling a large number of accelerators and processors in a shared memory cluster is a challenging task, since the complexity of the resulting system quickly becomes too large. We tackle these issues by proposing a template of heterogeneous shared memory cluster which scales to a large number of accelerators, achieving up to 40% better performance/area/watt than simply designing larger main interconnects to accommodate several HW IPs. In addition, following a trend towards standardization of acceleration capabilities of future embedded systems, we develop a programming model which simplifies application development for heterogeneous clusters.

关键词： Parallel architectures

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A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool

A coarse-grained reconfigurable wavelet denoiser exploiting ...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Carta, Nicola Sau, Carlo Palumbo, Francesca Pani, Danilo Raffo, Luigi DIEE - Dept. of Electrical and Electronic Engineering University of Cagliari P.zza D'Armi 09123 Cagliari Italy

ISBN: (纸本)9791092279016

In the last few years, efficient resource management turned out to be one of the major challenges for hardware designers. Strategies of reusability through reconfiguration have demonstrated interesting potentials to address it, providing also power and area minimization. The Multi-Dataflow Composer (MDC) tool has been presented to the scientific community to automatically build-up runtime coarse-grained reconfigurable platforms. Originally conceived in the field of Reconfigurable Video Coding (RVC), the MDC allows achieving attractive results also for hardware designers operating in different application fields. In this work, we intend to demonstrate the potential orthogonality of the MDC approach with respect to the RVC domain. A runtime reconfigurable wavelet denoiser, targeted for biomedical applications, has been developed and prototyped onto an FPGA Development Board Spartan 3E 1600. Impressive results in terms of resource minimization have been achieved with respect to more traditional solutions.

关键词： Video signal processing

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design space exploration and implementation of RVC-CAL applications using the TURNUS framework

Design space exploration and implementation of RVC-CAL appli...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Casale-Brunet, S. Bezati, E. Alberti, C. Roquier, G. Mattavelli, M. Janneck, J.W. Boutellier, J. SCI-STI-MM Multimedia Group École Polytechnique Fédérale de Lausanne Switzerland Department of Computer Science Lund University Sweden Department of Computer Science and Engineering University of Oulu Finland

ISBN: (纸本)9791092279016

While research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support has not emerged so far, and thus the creation of such systems remains a difficult, time-consuming and error-prone process. The absence of principled support for system evaluation and optimization at high abstraction levels makes the quality of the resulting implementation highly dependent on the experience or prejudices of the designer. In this work we present TURNUS, a unified dataflow design space exploration framework for heterogeneous parallel systems. It provides high-level modelling and simulation methods and tools for system level performances estimation and optimization. TURNUS represents the outcome of several years of research in the area of co-design exploration for multimedia stream applications. During the presentation, it will be demonstrated how the initial high-level abstraction of the design facilitates the use of different analysis and optimization heuristics. These guide the designer during validation and optimization stages without requiring low-level implementations of parts of the application. Our framework currently yields exploration and optimization results in terms of algorithmic optimization, rapid performance estimation, application throughput, buffer size dimensioning, and power optimization.

关键词： Optimization

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Proceedings of the 2011 conference on design and architectures for signal and image processing, dasip 2011

Proceedings of the 2011 Conference on Design and Architectur...

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2011 conference on design and architectures for signal and image processing, dasip 2011

ISBN: (纸本)9781457706196

The proceedings contain 45 papers. The topics discussed include: performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach;design of a processor optimized for syntax parsing in video decoders;fast and accurate hybrid power estimation methodology for embedded systems;acceleration of image reconstruction in 3D ultrasound computer tomography: an evaluation of CPU, GPU and FPGA computing;DFG implementation on multi GPU cluster with computation-communication overlap;graphic rendering application profiling on a shared memory MPSoC architecture;pilot studies of wireless sensor networks: practical experiences;efficient FFT pruning algorithm for non-contiguous OFDM systems;designing processors using MAsS, a modular and lightweight instruction-level exploration tool;and optimization methodologies for complex FPGA-based signal processing systems with CAL.

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Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform

Noise-agnostic adaptive image filtering without training ref...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Mora, Javier Gallego, Ángel Otero, Andrés De La Torre, Eduardo Riesgo, Teresa Centro de Electrónica Industrial Universidad Politécnica de Madrid Madrid Spain

ISBN: (纸本)9791092279016

One of the main concerns of evolvable and adaptive systems is the need of a training mechanism, which is normally done by using a training reference and a test input. The fitness function to be optimized during the evolution (training) phase is obtained by comparing the output of the candidate systems against the reference. The adaptivity that this type of systems may provide by re-evolving during operation is especially important for applications with runtime variable conditions. However, fully automated self-adaptivity poses additional problems. For instance, in some cases, it is not possible to have such reference, because the changes in the environment conditions are unknown, so it becomes difficult to autonomously identify which problem requires to be solved, and hence, what conditions should be representative for an adequate re-evolution. In this paper, a solution to solve this dependency is presented and analyzed. The system consists of an image filter application mapped on an evolvable hardware platform, able to evolve using two consecutive frames from a camera as both test and reference images. The system is entirely mapped in an FPGA, and native dynamic and partial reconfiguration is used for evolution. It is also shown that using such images, both of them being noisy, as input and reference images in the evolution phase of the system is equivalent or even better than evolving the filter with offline images. The combination of both techniques results in the completely autonomous, noise type/level agnostic filtering system without reference image requirement described along the paper.

关键词： Cameras

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Accuracy and performance analysis of Harris corner computation on tightly-coupled processor arrays

Accuracy and performance analysis of Harris corner computati...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Sousa, Éricles Rodrigues Tanase, Alexandru Hannig, Frank Teich, Jürgen Hardware/Software Co-Design Department of Computer Science University of Erlangen-Nuremberg Germany

ISBN: (纸本)9791092279016

Nowadays, computer vision algorithms have countless application domains. On the one hand, these algorithms are typically computationally demanding, on the other hand, they are often used in embedded systems, which have stringent constraints on, e. g., size or power. In this work, we present the benefits of mapping compute-intensive imaging algorithms on programmable massively parallel processor arrays. More specific, we propose different variants of a combined corner and edge detection algorithm, the Harris Corner Detector (HCD), map these variants onto tightly-coupled processor arrays (TCPAs), and prototype the TCPA architecture, executing the different HCD implementations, in FPGA technology. Because floating-point operations are very costly in FPGAs, we use fixed-point arithmetic in our design, and evaluate our implementation by means of accuracy and performance against two state-of-the-art implementations: (a) the OpenCV library of programming functions for real-time computer vision, using 64-bit floating-point precision, and (b) a 32-bit fixed-point DSP-based embedded system. The accuracy of our work is evaluated by considering the number of corners detected. Here, our approach achieves an average error of less than 1.5% when compared with a reference implementation. Our different variants, trading accuracy for performance, are mapped to the programmable processor elements of a TCPA. Here, the fastest TCPA implementation achieves a 55 times higher frame rate than a state-of-the-art implementation of the HCD on a digital signal processor. Finally, we show how our implementation can be used in the context of a new resource-aware parallel computing paradigm, called invasive computing. Here, an application can adapt itself at run-time in order to satisfy different quality and throughput requirements.

关键词： Embedded systems

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XMSIM: A tool for early memory hierarchy evaluation

XMSIM: A tool for early memory hierarchy evaluation

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Dimitroulakos, Grigoris Lioris, Theodoros Lezos, Christakis Masselos, Konstantinos University of Peloponnese Department of Computer Science and Technology Terma Karaiskaki 22100 Tripoli Greece

In this demonstration we present the usage of XMSIM, a tool for memory hierarchy evaluation of multimedia applications. The input is a high level C code application description and a memory hierarchy specification and... 详细信息

ISBN: (纸本)9782953998726

关键词： Computer aided design

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