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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"
266 条 记 录,以下是181-190 订阅
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designing processors using MAsS, a modular and lightweight instruction-level exploration tool
Designing processors using MAsS, a modular and lightweight i...
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conference on design and architectures for signal and image processing
作者: Matthieu Texier Erwan Piriou Mathieu Thevenin Raphaël David LIST Embedded Computing Laboratory CEA Gif-sur-Yvette France
As application complexity increases, the design of efficient computing architectures able to cope with embedded constraints requires a fine algorithm analysis. This paper proposes an original approach based on Modular... 详细信息
来源: 评论
Demo: Overlay architectures for heterogeneous FPGA cluster management
Demo: Overlay architectures for heterogeneous FPGA cluster m...
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conference on design and architectures for signal and image processing
作者: Théotime Bollengier Mohamad Najem Jean-Christophe Le Lann Loïc Lagadec b<>com Brest France Lab-STICC MOCS ENSTA Bretagne Brest France
Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features in... 详细信息
来源: 评论
FPGA implementations of HEVC Inverse DCT using high-level synthesis
FPGA implementations of HEVC Inverse DCT using high-level sy...
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conference on design and architectures for signal and image processing
作者: Ercan Kalali Ilker Hamzaoglu Faculty of Engineering and Natural Sciences Sabanci University Istanbul Tuzla Turkey
High Efficiency Video Coding (HEVC), the recently developed international video compression standard, has 50% better video compression efficiency than H.264 video compression standard at the expense of significantly i... 详细信息
来源: 评论
Session 2: architectures for image processing
Session 2: Architectures for image processing
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conference on design and architectures for signal and image processing
作者: Francesca Palumbo Università degli Studi di Sassari (Italy)
In the field of signal processing in general, and in particular in the image processing one, it is quite common to customize the underling architecture to improve computing efficiency. This section is dedicated to Arc... 详细信息
来源: 评论
On-chip compression for HDR image sensors
On-chip compression for HDR image sensors
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conference on design and architectures for signal and image processing
作者: Fadoua Guezzi Messaoud Arnaud Peizerat Antoine Dupret Yves Blanchard L3I-MINATEC CEA-LETI Grenoble France ESYCOM ESIEE Paris Paris-Est University Noisy le Grand France
An image compressing technique for High Dynamic Range (HDR) image sensors is introduced. Compression is performed in two steps: Pixel value coding optimization followed by DCT-based (Discrete Cosine Transform) compres... 详细信息
来源: 评论
A framework for the design of reconfigurable fault tolerant architectures
A framework for the design of reconfigurable fault tolerant ...
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conference on design and architectures for signal and image processing
作者: Hung Manh Pham Sébastien Pillement Olivier Pasquier Sébastien Le Nours University of Rennes 1/IRISA Lannion France IREENA Polytech Nantes Nantes France
The rapid evolutions in reconfigurable electronic products design permit to handle more and more complex applications. New fields of investigations (i.e. automotive, aerospatial, banking,...) are interesting but requi... 详细信息
来源: 评论
FPGA Implementation for GPR signal processing Based on HW/SW Co-design Architecture
FPGA Implementation for GPR Signal Processing Based on HW/SW...
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IEEE conference on Antenna Measurements (CAMA)
作者: Srimuk, Pachara Boonpoonga, Akkarat Burintramart, Santana King Mongkuts Univ Technol North Bangkok Fac Engn Dept Elect & Comp Engn Elect Engn Bangkok Thailand Minist Def Def Technol Inst Publ Org Pakkret 11120 Nontburi Thailand
This paper proposes a field programmable gate array (FPGA) implementation for signal processing of a ground penetrating radar (GPR). The signal processing includes zero offset removal and clutter reduction. The implem... 详细信息
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architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology
Architectures and signal reconstruction methods for nanoseco...
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conference on design and architectures for signal and image processing
作者: Martin Zlatanski Wilfried Uhring Virginie Zint Jean-Pierre Le Normand Daniel Mathiot Institut d'Electronique du Solide et des Systèmes CNRS Université de Strasbourg Strasbourg France
This paper presents the state of the art of the Integrated Streak Camera (ISC) architectures in standard CMOS technology. It focuses on some of the methods required for reconstructing the luminous events profile from ... 详细信息
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Multiple Transform Selection concept modeling and implementation using Interface Based SDF graphs  21
Multiple Transform Selection concept modeling and implementa...
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14th Workshop on design and architectures for signal and image processing, dasip 2021, held jointly with the 16th HiPEAC conference
作者: Haggui, Naouel Belghith, Fatma Hamidouche, Wassim Masmoudi, Nouri Nezan, Jean-François Ietr Laboratory Insa Rennes France National School of Engineering of Sfax Tunisia
Recent studies predict that video data accounts for 82% of Internet traffic by 2022. This fact has motivated MPEG to define a new Video Coding Standard called Versatile Video Coding (VVC), which will be released by th... 详细信息
来源: 评论
Demo: SLP-aware word length optimization
Demo: SLP-aware word length optimization
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conference on design and architectures for signal and image processing
作者: Ali Hassan El Moussawi Steven Derrien Avenue Général Leclerc Université de Rennes1 Rennes
Many embedded processors do not support floating-point arithmetic. But they generally provide support for SIMD as a mean to improve performance for near-zero cost overhead. Achieving good performance when targeting su... 详细信息
来源: 评论