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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是181-190 订阅

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designing processors using MAsS, a modular and lightweight instruction-level exploration tool

Designing processors using MAsS, a modular and lightweight i...

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conference on design and architectures for signal and image processing

作者： Matthieu Texier Erwan Piriou Mathieu Thevenin Raphaël David LIST Embedded Computing Laboratory CEA Gif-sur-Yvette France

As application complexity increases, the design of efficient computing architectures able to cope with embedded constraints requires a fine algorithm analysis. This paper proposes an original approach based on Modular Assembly Simulator (MAsS) tool that allows design Space Exploration (DSE) for programmable processors. The originality of the method resides in its capacity to generate operator level simulators allowing a quick code analysis from real data sets. This paper also presents two successfully designed architectures using MAsS.

关键词： Program processors Computer architecture Registers Kernel VLIW Parallel processing Algorithm design and analysis

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Demo: Overlay architectures for heterogeneous FPGA cluster management

Demo: Overlay architectures for heterogeneous FPGA cluster m...

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conference on design and architectures for signal and image processing

作者： Théotime Bollengier Mohamad Najem Jean-Christophe Le Lann Loïc Lagadec b<>com Brest France Lab-STICC MOCS ENSTA Bretagne Brest France

ISBN: (纸本)9781509030859

Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features independent from the host FPGA. We designed a fine-grained overlay implementing novel features easing the management of such architectures in a cluster of heterogeneous COTS FPGAs. This demonstration shows the use of this overlay in an FPGA cluster, performing a hardware application live migration between two nodes of a cluster. It also illustrates fault tolerance of the cluster.

关键词： Field programmable gate arrays Hardware Program processors Hardware design languages Fault tolerance Fault tolerant systems Table lookup

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FPGA implementations of HEVC Inverse DCT using high-level synthesis

FPGA implementations of HEVC Inverse DCT using high-level sy...

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conference on design and architectures for signal and image processing

作者： Ercan Kalali Ilker Hamzaoglu Faculty of Engineering and Natural Sciences Sabanci University Istanbul Tuzla Turkey

High Efficiency Video Coding (HEVC), the recently developed international video compression standard, has 50% better video compression efficiency than H.264 video compression standard at the expense of significantly increased computational complexity. HEVC Inverse Discrete Cosine Transform (IDCT) algorithm accounts for 11% of the computational complexity of an HEVC video encoder. Recently, commercial and academic high-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementations of HEVC 2D IDCT algorithm using HLS tools in the literature are proposed. The proposed HEVC IDCT hardware are implemented on Xilinx FPGAs using three HLS tools; Xilinx Vivado HLS, LegUp, MATLAB Simulink HDL Coder. Using HLS tools significantly reduced the FPGA development time, and the resulting FPGA implementations achieved real-time performance. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.

关键词： Hardware design languages Field programmable gate arrays MATLAB Standards Video compression Discrete cosine transforms

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Session 2: architectures for image processing

Session 2: Architectures for image processing

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conference on design and architectures for signal and image processing

作者： Francesca Palumbo Università degli Studi di Sassari (Italy)

ISBN: (纸本)9781509030859

In the field of signal processing in general, and in particular in the image processing one, it is quite common to customize the underling architecture to improve computing efficiency. This section is dedicated to architectures for image processing and four different papers will be presented. Solutions based on application specific processors, characterized on the processing requirements, may improve on board processing and facilitate data transmission from distributed computing nodes as presented in first paper. Memory hierarchy implementation and management is fundamental to improve computing efficiency. In this sense, the second paper investigates the usage of associative memories for pattern detection purposes and will apply them in the context of Clustered Neural Networks, while the third one presents a memory efficient architecture implementing in hardware the Multi-Scale Line Detector algorithm for real-time retinal blood vessel detection. Finally, the last paper is more system oriented, being focused on modelling techniques to derive and verify lossless compression IP cores.

关键词： image processing ARCHITECTURE Application specific processors Building construction data transmission signal processing paper Associative memory Solutions Memory Retinal Vessels

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On-chip compression for HDR image sensors

On-chip compression for HDR image sensors

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conference on design and architectures for signal and image processing

作者： Fadoua Guezzi Messaoud Arnaud Peizerat Antoine Dupret Yves Blanchard L3I-MINATEC CEA-LETI Grenoble France ESYCOM ESIEE Paris Paris-Est University Noisy le Grand France

An image compressing technique for High Dynamic Range (HDR) image sensors is introduced. Compression is performed in two steps: Pixel value coding optimization followed by DCT-based (Discrete Cosine Transform) compression. A floating point coding technique is first used with a common exponent shared between pixels of the same block, and then a DCT is applied to each group of pixels. This new concept, while maintaining low complexity architecture, shows a compression ratio of 75 % and retains a good image quality with a PSNR of about 40 dB.

关键词： image coding Pixel PSNR Discrete cosine transforms Encoding image sensors image reconstruction

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A framework for the design of reconfigurable fault tolerant architectures

A framework for the design of reconfigurable fault tolerant ...

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conference on design and architectures for signal and image processing

作者： Hung Manh Pham Sébastien Pillement Olivier Pasquier Sébastien Le Nours University of Rennes 1/IRISA Lannion France IREENA Polytech Nantes Nantes France

The rapid evolutions in reconfigurable electronic products design permit to handle more and more complex applications. New fields of investigations (i.e. automotive, aerospatial, banking,...) are interesting but require a high level of dependability. This paper proposes a framework to design reconfigurable architecture supporting fault-tolerance mitigation scheme. The proposed framework allows simulation, validation of mitigation operations, but also to size architecture resources. The implementation of a fault-tolerant reconfigurable platform permits to validate the proposed model and the effectiveness of the framework. This implementation shows the potential of dynamically reconfigurable architectures for supporting fault-tolerance in embedded systems.

关键词： Computer architecture Circuit faults Redundancy Field programmable gate arrays Fault tolerant systems Synchronization

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FPGA Implementation for GPR signal processing Based on HW/SW Co-design Architecture

FPGA Implementation for GPR Signal Processing Based on HW/SW...

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IEEE conference on Antenna Measurements (CAMA)

作者： Srimuk, Pachara Boonpoonga, Akkarat Burintramart, Santana King Mongkuts Univ Technol North Bangkok Fac Engn Dept Elect & Comp Engn Elect Engn Bangkok Thailand Minist Def Def Technol Inst Publ Org Pakkret 11120 Nontburi Thailand

ISBN: (纸本)9781467391498

This paper proposes a field programmable gate array (FPGA) implementation for signal processing of a ground penetrating radar (GPR). The signal processing includes zero offset removal and clutter reduction. The implementation is based on the hardware and software (HW/SW) co-design. The hardware structures are introduced for performing zero offset removal and clutter reduction. The hardware structures are constructed with a basic processing elements such as multipliers and adders etc. Software designed on MicroBlaze is employed to control the hardware architectures and data flows including reading and writing memories. The design architectures including hardware and software is implemented on a Xilinx Zynq-7000 All Programmable SoC XC7Z020-CLG484-1 FPGA device. Experimental results based on the FPGA device are given to examine the performance of the proposed implementation. The B-scan GPR image are shown to demonstrate the ability of the proposed architecture. Preliminary experimentations show good agreement between implementation and simulation.

关键词： FPGA Co-design HW/SW GPR

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architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology

Architectures and signal reconstruction methods for nanoseco...

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conference on design and architectures for signal and image processing

作者： Martin Zlatanski Wilfried Uhring Virginie Zint Jean-Pierre Le Normand Daniel Mathiot Institut d'Electronique du Solide et des Systèmes CNRS Université de Strasbourg Strasbourg France

This paper presents the state of the art of the Integrated Streak Camera (ISC) architectures in standard CMOS technology. It focuses on some of the methods required for reconstructing the luminous events profile from the chip raw data. Two main ISC architectures are presented. The first adopts the traditional for the most silicon imagers pixel array configuration, where the photocharges-induced signal is processed directly in-pixel. The second approach is based on a single light detecting vector, comparable to the slit of a Conventional Streak Camera (CSC), coupled to an amplifier stage and an analog sampling and storage unit. For both architectures, depending on the on-chip processing of the photocharges, appropriate signal reconstruction techniques are required in order to restore the luminous signal shape. A novel single vector ISC front-end architecture with an asynchronous photodiode reset scheme is presented. Algorithms allowing the luminous event reconstruction are proposed and validated through simulations for all the ISCs considered.

关键词： Pixel Photodiodes Optical sensors Cameras Optical imaging Delay image reconstruction

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Multiple Transform Selection concept modeling and implementation using Interface Based SDF graphs 21

Multiple Transform Selection concept modeling and implementa...

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14th Workshop on design and architectures for signal and image processing, dasip 2021, held jointly with the 16th HiPEAC conference

作者： Haggui, Naouel Belghith, Fatma Hamidouche, Wassim Masmoudi, Nouri Nezan, Jean-François Ietr Laboratory Insa Rennes France National School of Engineering of Sfax Tunisia

ISBN: (纸本)9781450389013

Recent studies predict that video data accounts for 82% of Internet traffic by 2022. This fact has motivated MPEG to define a new Video Coding Standard called Versatile Video Coding (VVC), which will be released by the end of 2020. VVC will offer the possibility to handle new video formats and to improve significantly video compression over its predecessor HEVC. Indeed, the objective is to reduce the necessary bit rate by half, at equivalent quality. These advances require the use of more complex algorithms, although the increase in complexity has been limited throughout the standardization process. In order to decrease the complexity of VVC and consequently the coding execution time, several methods have been introduced at different stages of the encoder. The aim of this paper is to explore the available parallelism of VVC to accelerate the coding and the decoding processes. This paper focuses on the transformation block and more specifically the new concept of Multiple Transform Selection (MTS) introduced by VVC. Moreover, a study of several granularity levels of Interface-Based Synchronous Dataflow (IBSDF) models and their impact on the performances obtained on x86 architectures is presented. IBSDF dataflow graph has been developed to reveal the available parallelism of MTS. The PREESM fast prototyping tool is then used for the mapping and the scheduling of MTS on virtual and real parallel architectures and for generating efficient parallel implementations on real architectures. PREESM has been used in this work to explore the potential parallelism offered by MTS and to prove the efficiency of MTS on multicore x86 architectures. Experimental results show a speed-up close to the optimum. © 2021 ACM.

关键词： Video signal processing

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Demo: SLP-aware word length optimization

Demo: SLP-aware word length optimization

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conference on design and architectures for signal and image processing

作者： Ali Hassan El Moussawi Steven Derrien Avenue Général Leclerc Université de Rennes1 Rennes

ISBN: (纸本)9781509030859

Many embedded processors do not support floating-point arithmetic. But they generally provide support for SIMD as a mean to improve performance for near-zero cost overhead. Achieving good performance when targeting such processors requires the use of fixed-point arithmetic and efficient SIMDization. To reduce applications time-to-market, automatic SIMDization and floating-point conversion methodologies have been proposed. In this paper we show that these two problems are strongly related and should be considered jointly. We briefly present a new SLP-aware floating-point conversion flow.

关键词： Program processors Dynamic range Optimization Quantization (signal) Computational modeling Parallel processing Context

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