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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是191-200 订阅

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An FPGA softcore based implementation of a bird call recognition system for sensor networks

An FPGA softcore based implementation of a bird call recogni...

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conference on design and architectures for signal and image processing

作者： Hongzhi Liu Neil W. Bergmann School of ITEE University of Queensland Australia

To investigate the on-sensor processing capabilities of FPGAs, this paper presents a bird call recognition system based on linear predictive cepstral coefficients (LPCC) and dynamic time warping (DTW) algorithms for sensor network applications, and compares two different implementations on a Xilinx Spartan-3E FPGA with MicroBlaze soft processor. The experimental results show that compared to the software-only solution, the software / hardware (SW/HW) implementation with hardware coprocessor for DTW yields significant performance improvement by the factor of 13.8 and 33.4 respectively for two example inputs, and achieves about 31.1 times energy efficiency by using only 7.5% more power.

关键词： Field programmable gate arrays Hardware Software Birds Feature extraction Digital signal processing Energy efficiency

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Demo: SLP-aware word length optimization

Demo: SLP-aware word length optimization

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conference on design and architectures for signal and image processing

作者： Ali Hassan El Moussawi Steven Derrien Avenue Général Leclerc Université de Rennes1 Rennes

ISBN: (纸本)9781509030859

Many embedded processors do not support floating-point arithmetic. But they generally provide support for SIMD as a mean to improve performance for near-zero cost overhead. Achieving good performance when targeting such processors requires the use of fixed-point arithmetic and efficient SIMDization. To reduce applications time-to-market, automatic SIMDization and floating-point conversion methodologies have been proposed. In this paper we show that these two problems are strongly related and should be considered jointly. We briefly present a new SLP-aware floating-point conversion flow.

关键词： Program processors Dynamic range Optimization Quantization (signal) Computational modeling Parallel processing Context

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Session 4: Advanced hardware architectures

Session 4: Advanced hardware architectures

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conference on design and architectures for signal and image processing

作者： Morteza Biglari-Abhari University of Auckland (New-Zealand)

ISBN: (纸本)9781509030859

Using hardware architectures to improve performance and energy efficiency has been a key factor for application-specific optimisations. Latest Field Programmable Gate Arrays (FPGA) can not only be used as a reconfigurable hardware platform, they also provide hard core processors and other hard core IPs on the same chip to implement multiprocessor systems on chip, which can be tuned based on the target applications characteristics. In this session, the first two papers present the challenges and optimisations to use hardware architectures based on FPGA for wireless communication systems. In addition an investigation of the crosstalk effects on the Network on Chip energy consumption, as the main interconnection network in multiprocessor systems on chip, is presented.

关键词： hardware architecture Field programmable gate arrays ARCHITECTURE Computer hardware system-on-chip multiprocessor system on chip Hardware Platform Wireless communication systems Interconnection networks Multiprocessor

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Systemc modelization for fast validation of imager architectures

Systemc modelization for fast validation of imager architect...

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conference on design and architectures for signal and image processing

作者： Yves Blanchard Antoine Dupret Arnaud Peizerat ESYCOM ESIEE Paris Paris-Est University Noisy le Grand France LETI-MINATEC CEA Grenoble France

Development of smart CMOS imagers is a complex design task where the verification of an architecture composed of a matrix of pixels intermixed with analog and digital electronics is playing an important part. New generations of imager using 3D integration will allow even more processing to be done in-situ. Verification has to be done locally for the pixel and globally for the architecture. design exploration and validation problematic has shifted from mostly the analog domain to the validation of a complex SOC with millions of parallel processors, the pixels. In this paper we present a methodology using the SystemC language for the creation of fast models for validation and a first level evaluation of performance of large CMOS imager architectures.

关键词： Computational modeling Object oriented modeling Computer architecture Kernel Integrated circuit modeling Adaptation models Hardware

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DFG implementation on multi GPU cluster with computation-communication overlap

DFG implementation on multi GPU cluster with computation-com...

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conference on design and architectures for signal and image processing

作者： Sylvain Huet Vincent Boulos Vincent Fristot Luc Salvo GIPSA-lab UMR5216 CNRS/INPG UJF U.Stendhal GRENOBLE France

Nowadays, it is possible to build a multi-GPU supercomputer, well suited for implementation of digital signal processing algorithms, for a few thousand dollars. However, to achieve the highest performance with this kind of architecture, the programmer has to focus on inter-processor communications, tasks synchronization ... In this paper, we propose a design flow allowing an efficient implementation of a Digital signal processing (DSP) application specified as a Data Flow Graph (DFG) on a multi GPU computer cluster. We focus particularly on the effective implementation of communications by automating the computation-communication overlap, which can lead to significant speedups as shown in the presented benchmark. The approach is validated on a 3D granulometry application developed for research on materials.

关键词： Graphics processing unit Kernel Computers Computer architecture Synchronization Instruction sets Digital signal processing

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High speed Fp multipliers and adders on FPGA platform

High speed Fp multipliers and adders on FPGA platform

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conference on design and architectures for signal and image processing

作者： Santosh Ghosh Debdeep Mukhopadhyay Dipanwita Roy Chowdhury Department of Computer Science & Engineering Indian Institute of Technology Kharagpur West Bengal India Department of Computer Science & Engineering Indian Institute of Technology Kharagpur Kharagpur West Bengal India

The paper proposes high speed FPGA implementations of adders and multipliers in F p . The work shows through experimental results that due to optimized addition chain available in such devices, Karatsuba decomposition upto a particular level improves the performance. Further the paper modifies existing interleaved multiplier using Montgomery ladder and the high speed adder circuits. Extensive experiments have been performed. The result shows that the proposed design provides 70% speedup from the best known designs.

关键词： Adders Field programmable gate arrays Algorithm design and analysis Performance evaluation Computer architecture Elliptic curves Registers

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Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip

Evaluation of analog and digital signal processing on PSoC a...

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conference on design and architectures for signal and image processing

作者： Stephan Werner Bernhard Stiehle Jürgen Becker Karlsruhe Institute of Technology (KIT) Institute for Information Processing Technologies (ITIV) Karlsruhe Germany

One trend for signal processing hardware is the increasing integration of different functionalities in one mixed-signal chip. But the additional integration of analog components on one chip with digital components and a micro-processor like in the Programmable System on Chip (PSoC) from Cypress is accompanied with the extension of the design space and the need to explore it by evaluating different implementations with the same functionality to find a good trade-off between analog and digital signal processing. This paper evaluates different implementations of the discrete cosine transform (DCT) with different analog-digital partitioning. Therefore the DCT is integrated as software controlled analog circuit based on the switched capacitors and operational amplifiers available in the analog subsystem of the PSoC architecture. The presented analog DCT implementation scales linear and the number of simultaneously computable spectral signal components is only limited by the available on-chip resources on the currently used PSoC5LP. To evaluate the analog implementation, the DCT is also implemented as software executed on the ARM Cortex-M3 integrated in the PSoC5LP. The comparison of both solutions shows that the analog hardware available on the PSoC architecture can be used to directly process analog sensor signals with only minor additional off-chip components with a CPU load of about 8% caused by the software controlling the analog subsystem.

关键词： Discrete cosine transforms Software Capacitors Computer architecture System-on-chip Hardware Electronics packaging

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Dual-core reconfigurable demosaicing engine for next generation of portable camera systems

Dual-core reconfigurable demosaicing engine for next generat...

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conference on design and architectures for signal and image processing

作者： Xin Zhao Ying Yi Ahmet T Erdogan Tughrul Arslan School of Engineering Kings Buildings University of Edinburgh Edinburgh UK

This paper presents a high performance dual-core reconfigurable processor implementation methodology for a demosaicing system that targets next generation camera systems. The implementation methodology is based on dual-core architecture with coarse-grained dynamically reconfigurable processors. The demosaicing system adopts Freeman's algorithm that has been partitioned and mapped onto two customized and tailored heterogeneous processor cores. The demosaicing engine's implementation has been optimized by compilation techniques and special approaches for the targeting processor. Simulation results demonstrate that the resulting demosaicing system provides high throughput reaches up to 241.6Mpixels/s, which represents a 1.82x speedup compared to a single-core implementation.

关键词： image color analysis Pixel Pipeline processing Kernel Filtering Multicore processing

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A unified hardware/software co-synthesis solution for signal processing systems

A unified hardware/software co-synthesis solution for signal...

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conference on design and architectures for signal and image processing

作者： Endri Bezati Hervé Yviquel Michaél Raulet Marco Mattavelli Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland IRISA University of Rennes I Lannion France IETR INSA Rennes Rennes France

This paper presents a methodology to specify from a high-level data-flow description an application for both hardware and software synthesis. Firstly, an introduction to RVC-Cal data-flow programming and Orcc framework is presented. Furthermore, an analysis of a close to gate intermediate representation (XLIM) is bestowed. As a proof of concept a JPEG codec was written purely in RVC-Cal to test the co-synthesis tools and then an analysis of the generated hardware and software results are given. Our experience shows that using RVC-Cal can unify the process of creating the same application for software and hardware without modifying a single source code for each solution.

关键词： Transform coding Hardware Codecs Software Decoding Field programmable gate arrays Hardware design languages

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Worst-case latency analysis of SDF-based parametrized dataflow MoCs

Worst-case latency analysis of SDF-based parametrized datafl...

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conference on design and architectures for signal and image processing

作者： Mladen Skelin Marc Geilen Francky Catthoor Sverre Hendseth Norwegian University of Science and Technology Eindhoven University of Technology MEC vzw

Modern-day streaming digital signal processing (DSP) applications are often accompanied by real-time requirements. In addition, they expose increasing levels of dynamic behavior. Dynamic dataflow models of computation (MoCs) have been introduced to model and analyze such applications. Parametrized dataflow MoCs are an important subclass of dynamic dataflow MoCs because they integrate dynamic parameters and run-time adaptation of parameters in a structured way. However, these MoCs have been primarily analyzed for functional behavior and correctness while the analysis of their temporal behavior has received little attention. In this work, we present a new analysis approach that allows analysis of worst-case latency for dynamic streaming DSP applications that can be captured using parametrized dataflow MoCs based on synchronous dataflow (SDF). We show that in the presence of parameter inter-dependencies our technique can yield tighter worst-case latency estimates than the existing techniques that operate on SDF structures that abstract the worst-case behaviour of the initial parametrized specifications. We base the approach on the (max,+) algebraic semantics of timed SDF and on its non-parametric generalization known as FSM-based scenario-aware dataflow (FSM-SADF). We evaluate the approach on a realistic case study from the multimedia domain.

关键词： Decoding Delays Digital signal processing Computational modeling Multimedia communication Adaptation models Streaming media

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