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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是211-220 订阅

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Runtime adaptive allocation of dynamically mixed tasks on a heterogeneous MPSoC platform

Runtime adaptive allocation of dynamically mixed tasks on a ...

引用

conference on design and architectures for signal and image processing

作者： Jia Huang Andreas Raabe Christian Buckl Alois Knoll Fortiss GmbH Munich Germany Technische Universität München Garching Germany

Multiprocessor System-on-Chip platforms are typically used for co-hosting multiple tasks, which may start and stop execution independently at time instants unknown at design time. In such systems, the runtime resource manager is responsible for allocating adequate and appropriate resources to each task. We identify a key issue in existing work that the resource management algorithms consider the problem only at task-level, i.e. the optimization is performed for each individual task upon activation. However, it can be shown that such strategies are suboptimal from the system point of view. In contrast, we propose in this paper a new task allocation flow that considers the system-level resource management. Comparing with traditional techniques, significant performance improvement (up to 29.5%) is observed during evaluation using a standard benchmark set. In addition, the proposed task allocator features runtime self-adaptability with respect to changes in hardware and/or applications.

关键词： Resource management Runtime Bandwidth Digital signal processing Timing Tiles Processor scheduling

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Low power design methodology for signal processing systems using lightweight dataflow techniques

Low power design methodology for signal processing systems u...

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conference on design and architectures for signal and image processing

作者： Lin Li Tiziana Fanni Timo Viitanen Renjie Xie Francesca Palumbo Luigi Raffo Heikki Huttunen Jarmo Takala Shuvra S. Bhattacharyya ECE Department University of Maryland MD USA Dept. of Electrical and Electronic Engineering University of Cagliari Italy Tampere University of Technology Finland University of Sassari PolComIng - Information Engineering Unit Italy

ISBN: (纸本)9781509030859

Dataflow modeling techniques facilitate many aspects of design exploration and optimization for signal processing systems, such as efficient scheduling, memory management, and task synchronization. The lightweight dataflow (LWDF) programming methodology provides an abstract programming model that supports dataflow-based design and implementation of signal processing hardware and software components and systems. Previous work on LWDF techniques has emphasized their application to DSP software implementation. In this paper, we present new extensions of the LWDF methodology for effective integration with hardware description languages (HDLs), and we apply these extensions to develop efficient methods for low power DSP hardware implementation. Through a case study of a deep neural network application for vehicle classification, we demonstrate our proposed LWDF-based hardware design methodology, and its effectiveness in low power implementation of complex signal processing systems.

关键词： Hardware design languages Ports (Computers) Hardware Digital signal processing design methodology Programming Standards

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FPGA memory optimization for real-time imaging

FPGA memory optimization for real-time imaging

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conference on design and architectures for signal and image processing

作者： Dominique Houzet Virginie Fresse Hubert Konik CNRS GIPSA-Lab Grenoble France UJM Saint Etienne Laboratoire Hubert Curien Saint Etienne France

ISBN: (纸本)9781509030859

Most of advanced driver assistance systems are developed for safety and better driving. Safety system using image processing, like Hough transform, requires a lot of memory whose underutilization can lead to decrease the real time performances. Internal memories on reconfigurable devices such as FPGA are limited in size, number and bandwidth. Memory optimization cannot be done solely at the application level. Holistic design-space exploration is necessary to leverage the inherent locality of applications and reduce memory accesses. In this paper, we target FPGA internal memories optimization by adding a small register-based multi-ported cache memory in front of each internal FPGA memory block to increase their bandwidth. The dimensions of this cache are explored according to the locality of the function implemented. The exploration uses a cumulative-write cache exhibiting 1.5 to 2 speedup compared to the best FPGA implementations. The solution is optimized with an identical number of memory and few added registers and LUT.

关键词： Random access memory Field programmable gate arrays Transforms image edge detection Registers Hardware Optimization

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The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer

The Multi-Dataflow Composer tool: A runtime reconfigurable H...

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conference on design and architectures for signal and image processing

作者： Francesca Palumbo Nicola Carta Luigi Raffo DIEE-Department of Electrical and Electronic Engineering University of Cagliari Cagliari Italy

Dataflow Model of Computation (D-MoC) is particularly suitable to close the gap between hardware architects and software developers. Leveraging on the combination of the D-MoC with a coarse-grained reconfigurable approach to hardware design, we propose a tool, the Multi-Dataflow Composer (MDC) tool, able to improve time-to-market of modern complex multi-purpose systems by allowing the derivation of HDL runtime reconfigurable platforms starting from the D-MoC models of the targeted set of applications. MDC tool has proven to provide a considerable on-chip area saving: the 82% of saving has been reached combining of different applications in the image processing domain, adopting a 90 nm CMOS technology. In future the MDC tool, with a very small integration effort, will also be extremely useful to create multi-standard codec platforms for MPEG RVC applications.

关键词： Kernel Hardware Hardware design languages Runtime Table lookup Switches Computational modeling

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High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

High level design space exploration of RVC codec specificati...

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conference on design and architectures for signal and image processing

作者： Christophe Lucarz Ghislain Roquier Marco Mattavelli Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++). As we are entering in the multicore era, sequential programs are no longer the most appropriate way to specify algorithms targeted to run on several processing units. The new ISO/MPEG Reconfigurable Video Coding (RVC) standard is proposing a new paradigm for specifying and designing complex signal processing systems. The RVC standard enables specifying new codecs by assembling blocks, or so called Functional Units (FUs) from a standard Video Tool Library (VTL). Flexibility, reusability, and modularity are the key features of RVC. This new way of specifying algorithms clearly simplifies the task of designing future video coding applications by allowing software and hardware reuse across multiple video coding standards. Specifications are provided in the form of an actor and dataflow-based language called CAL. Although the RVC standard does not imply any specific implementation design flow, it is an appropriate starting point for targeting multiple processing units platforms. This paper describes a new model-driven design flow which considers both algorithm and architecture to map RVC codec specifications onto heterogeneous and multi-core systems.

关键词： Algorithm design and analysis Processor scheduling Transform coding Software Throughput signal processing algorithms Measurement

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Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems

Hardware/software co-design of H.264/AVC encoders for multi-...

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conference on design and architectures for signal and image processing

作者： Tiago Dias Nuno Roma Leonel Sousa INESC-ID Lisbon ISEL-PI Lisbon Technical University of Lisbon IST Lisboa Portugal

This paper presents a multi-core H.264/AVC encoder suitable for implementations in small and medium complexity embedded systems. The proposed structure results from an efficient hardware/software co-design methodology, where the encoder software application is highly optimized and structured in a very modular and efficient manner, so as to allow its most complex and time consuming operations to be offloaded to dedicated hardware accelerators. The considered methodology adopts a simple and efficient core interconnection mechanism to easily allow the inclusion and the removal of such optimized processing cores. Experimental results obtained with the implementation in a Virtex4 FPGA of an H.264/AVC encoder using an ASIP IP core as a ME hardware accelerator have proven the advantages of this methodology. For the considered system, speedup factors greater than 15 were obtained with a very modest increase of the involved hardware resources.

关键词： Hardware Multicore processing Registers Automatic voltage control IP networks Embedded systems

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A new algorithm for realization of FIR filters using multiple constant multiplications

A new algorithm for realization of FIR filters using multipl...

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conference on design and architectures for signal and image processing

作者： Mohsen Amiri Farahani Eduardo Castillo-Guerra Bruce G. Colpitts Department of Electrical and Computer engineering University of New Brunswick Canada

This paper presents a new common subexpression elimination (CSE) algorithm to realize FIR filters based on multiple constant multiplications (MCMs). This algorithm shares the maximum number of partial terms amongst minimal signed digit (MSD)-represented coefficients. It modifies the iterated matching (ITM) algorithm to share more partial terms in MCMs, which yields a significant logic and, consequently, chip area savings. The employment of the proposed algorithm results in efficient realizations of FIR filters with a fewer number of adders compared to the conventional CSE algorithms. Experimental results demonstrate a reduction up to 22% in the complexity of FIR filters over some conventional CSE algorithms. The proposed algorithm also addresses challenges encountered in resource-constrained applications, which require banks of high-order filters, such as in real-time distributed optical fiber sensor.

关键词： Adders Finite impulse response filter Algorithm design and analysis Pattern matching Filtering algorithms Optical fiber filters Filtering theory

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Parallelization of an ultrasound reconstruction algorithm for non destructive testing on multicore CPU and GPU

Parallelization of an ultrasound reconstruction algorithm fo...

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conference on design and architectures for signal and image processing

作者： Antoine Pédron Lionel Lacassagne Franck Bimbard Stéphane Le Berre LIST CEA Gif-sur-Yvette France Institut d'Electronique Fondamentale UMR 8622 Université Paris-Sud 11 Orsay France

The CIVA software platform developed by CEA-LIST offers various simulation and data processing modules dedicated to non-destructive testing (NDT). In particular, ultrasonic imaging and reconstruction tools are proposed, in the purpose of localizing echoes and identifying and sizing the detected defects. Because of the complexity of data processed, computation time is now a limitation for the optimal use of available information. In this article, we present performance results on parallelization of one computationally heavy algorithm on general purpose processors (GPP) and graphic processing units (GPU). GPU implementation makes an intensive use of atomic intrinsics. Compared to initial GPP implementation, optimized GPP implementation runs up to ×116 faster and GPU implementation up to ×631. This shows that, even with irregular workloads, combining software optimization and hardware improvements, GPU give high performance.

关键词： Graphics processing unit Instruction sets image reconstruction Software algorithms Kernel Testing Optimization

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APPLICATIONS OF VEDIC MULTIPLIER designS A REVIEW 4

APPLICATIONS OF VEDIC MULTIPLIER DESIGNS A REVIEW

引用

4th International conference on Reliability, Infocom Technologies and Optimization (ICRITO)

作者： Kant, Akanksha Sharma, Shobha Indira Gandhi Delhi Tech Univ Women VSLI Design New Delhi India Indira Gandhi Delhi Tech Univ Women ECE New Delhi India

ISBN: (纸本)9781467372312

Rapidly growing technology has raised demands for fast and efficient real time digital signal processing applications. Multiplication is one of the primary arithmetic operations every application demands. A large number of multiplier designs have been developed to enhance their speed. Active research over decades has lead to the emergence of Vedic Multipliers as one of the fastest and low power multiplier over traditional array and booth multipliers. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. A large number of them have been proposed using Urdhava Tiryakbhyam sutra rendering them most efficient in terms of speed. The objective of this paper is to encapsulate an array of applications of Vedic Multiplier in the vast domain of image processing and Digital signal processing, particularly the different modifications of existing Vedic Multiplier architectures enhancing their speed and performance parameters.

关键词： Vedic Multiplier image processing Digital signal processing Urdhava Tiryakbhyam sutra

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Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing

Acceleration of image reconstruction in 3D ultrasound comput...

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conference on design and architectures for signal and image processing

作者： Matthias Birk Alexander Guth Michael Zapf Matthias Balzer Nicole Ruiter Michael Hübner Jürgen Becker Karlsruhe Institute of Technology Karlsruhe Germany

As today's standard screening methods frequently fail to diagnose breast cancer before metastases have developed, earlier breast cancer diagnosis is still a major challenge. Three-dimensional ultrasound computer tomography promises high-quality images of the breast, but is currently limited by a time-consuming synthetic aperture focusing technique based image reconstruction. In this work, we investigate the acceleration of the image reconstruction by a GPU, and by the FPGAs embedded in our custom data acquisition system. We compare the obtained performance results with a recent multi-core CPU and show that both platforms are able to accelerate processing. The GPU reaches the highest performance. Furthermore, we draw conclusions in terms of applicability of the accelerated reconstructions in future clinical application and highlight general principles for speed-up on GPUs and FPGAs.

关键词： Field programmable gate arrays Graphics processing unit image reconstruction Instruction sets Data acquisition Acceleration Kernel

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