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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是231-240 订阅

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Characterization of capture actions in video sequences

Characterization of capture actions in video sequences

引用

conference on design and architectures for signal and image processing

作者： Ana Pinzari Mohamed Shawky Heudiasyc Laboratory JRU CNRS Université de Technologie de Compiegne Compiegne France

This paper deals with automatic characterization of video capture actions like scale change (zoom) or translation (traveling) in a video sequence. The overall objective is to enhance the scripted quality while capturing a video sequence by professionals or non professionals. Ultimately, the capture actions would use a predefined video template, progressively filled by the cameraman and automatically checked against the template scenario by the acquisition system. We focused on the detection of the zoom action. The characteristics of zoom are detected by analyzing pairs of frames of the target sequence. The principle of the method resides in choosing characteristic points into a pair of images, matching them in order to estimate the plane projective transformation using RANSAC method. Once the transformation model has been found, it allows to extract relevant information regarding the scale and the translation factor, necessary to verify the type and also the quality of the realized zoom sequence. We present several experiments that show very promising results.

关键词： Cameras Video sequences Robustness Context image matching Pixel Estimation

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design and hardware implementation of a low-complexity multiuser vector precoder

Design and hardware implementation of a low-complexity multi...

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conference on design and architectures for signal and image processing

作者： Maitane Barrenechea Luis Barbero Mikel Mendicute John Thompson Department of Electronics and Computer Science University of Mondragrón Mondragon Spain Institute of Electronics Communications and Information Technology Queen''s University Belfast Belfast UK Institute of Digital Communications University of Edinburgh Edinburgh UK

In the multiuser MIMO broadcast channel, the use of precoding techniques is required in order to detect the signal at the users' terminals without any cooperation between them. This contribution presents the design and hardware implementation of a high-capacity precoder based on vector perturbation. The most challenging part of the vector precoding (VP) scheme, that is, the search for the perturbing signal in an infinite lattice, has been completed by the reduced-complexity albeit high-performance Fixed Sphere Encoder (FSE) algorithm. The most remarkable feature of the FSE is its fixed complexity, which makes it highly suitable for hardware implementation on field-programmable gate arrays (FPGA), where the parallelization and pipelining of resources can be applied to enhance the system throughput. An optimized reduced-complexity implementation is proposed, which achieves high performance with a reduced hardware resource usage.

关键词： Hardware Lattices Field programmable gate arrays Algorithm design and analysis Complexity theory MIMO Mathematical model

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Interfacing and scheduling legacy code within the Canals framework

Interfacing and scheduling legacy code within the Canals fra...

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conference on design and architectures for signal and image processing

作者： Andreas Dahlin Fareed Jokhio Johan Lilius Jérôme Gorin Michaël Raulet IETR/Image Group Laboratory INSA Rennes Rennes France Turku Centre for Computer Science Department of Information Technologies Åbo Akademi University Turku Finland

The need for understanding how to distribute computations across multiple cores, have obviously increased in the multi-core era. Scheduling the functional blocks of an application for concurrent execution requires not only a good understanding of data dependencies, but also a structured way to describe the intended scheduling. In this paper we describe how the Canals language and its scheduling framework can be used for the purpose of scheduling and executing legacy code. Additionally a set of translation guidelines for translating RVC-CAL applications into Canals are presented. The proposed approaches are applied to an existing MPEG-4 Simple Profile decoder for evaluation purposes. The inverse discrete cosine transform (IDCT) is accelerated by the means of OpenCL.

关键词： Irrigation Kernel Processor scheduling Schedules Network topology Computational modeling

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A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

A methodology for precise comparisons of processor core arch...

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conference on design and architectures for signal and image processing

作者： B. Rousseau Ph. Manet I. Loiselle J.-D. Legat H. Vandierendonck Laboratoire de microélectronique (DICE) Université Catholique de Louvain Louvain-la-Neuve Belgium Department ELIS/HiPEAC Ghent University Ghent Belgium

The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels.

关键词： Computer architecture Optimization VLIW Digital signal processing Reduced instruction set computing Microarchitecture Timing

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VIDEO ACTION RECOGNITION VIA NEURAL ARCHITECTURE SEARCHING 26

VIDEO ACTION RECOGNITION VIA NEURAL ARCHITECTURE SEARCHING

引用

26th IEEE International conference on image processing (ICIP)

作者： Peng, Wei Hong, Xiaopeng Zhao, Guoying Univ Oulu Ctr Machine Vision & Signal Anal Oulu Finland Xi An Jiao Tong Univ Xian Peoples R China

ISBN: (纸本)9781538662496

Deep neural networks have achieved great success for video analysis and understanding. However, designing a high-performance neural architecture requires substantial efforts and expertise. In this paper, we make the first attempt to let algorithm automatically design neural networks for video action recognition tasks. Specifically, a spatio-temporal network is developed in a differentiable space modeled by a directed acyclic graph, thus a gradient-based strategy can be performed to search an optimal architecture. Nonetheless, it is computationally expensive, since the computational burden to evaluate each architecture candidate is still heavy. To alleviate this issue, we, for the video input, introduce a temporal segment approach to reduce the computational cost without losing global video information. For the architecture, we explore in an efficient search space by introducing pseudo 3D operators. Experiments show that, our architecture outperforms popular neural architectures, under the training from scratch protocol, on the challenging UCF101 dataset, surprisingly, with only around one percentage of parameters of its manual-design counterparts.

关键词： Automated machine learning neural architecture search video action recognition

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Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms

Hardware/software co-design of dataflow programs for reconfi...

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conference on design and architectures for signal and image processing

作者： Ghislain Roquier Endri Bezati Richard Thavot Marco Mattavelli Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

The possibility of specifying both software and hardware components from a unified high-level description of an application is a very attractive design approach. However, despite the efforts spent for implementing such an approach using general purpose programming languages, it has not yet shown to be viable and efficient for complex designs. One of the reasons is that the sequential programming model does not naturally provide explicit and scalable parallelism and composability properties that effectively permits to build portable applications that can be efficiently mapped on different kind of heterogeneous platforms. Conversely dataflow programming is an approach that naturally provides explicit parallel programs with composability properties. This paper presents a methodology for the hardware/software co-design that enables, by direct synthesis of both hardware descriptions (HDL), software components (C/C++) and mutual interfaces, to generate an implementation of the application from an unique dataflow program, running onto heterogeneous architectures composed by reconfigurable hardware and multi-core processors. Experimental results based on the implementation of a JPEG codec onto an heterogeneous platform are also provided to show the capabilities and flexibility of the implementation approach.

关键词： Hardware Software Field programmable gate arrays Programming Multicore processing Hardware design languages

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Efficient FFT pruning algorithm for non-contiguous OFDM systems

Efficient FFT pruning algorithm for non-contiguous OFDM syst...

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conference on design and architectures for signal and image processing

作者： Roberto Airoldi Fabio Garzia Jari Nurmi Department of Computer Systems Tampere University of Technology Tampere Finland

This paper presents the study of an efficient trade-off between memory requirements and performance for the implementation of FFT pruning algorithm. FFT pruning algorithm is utilized in NC-OFDM systems to simplify the FFT algorithm complexity in presence of subcarrier sparseness. State-of-the-art implementations offer good performance with the drawback of high resources utilization, i.e. data memory for storage of the configuration matrix. In this work we introduce the partial pruning algorithm as an efficient way to implement FFT pruning, obtaining a balanced trade-off between performance and resources allocation. Cycle accurate simulation results showed that even in presence of low-medium input sparseness levels the proposed algorithm can reduce the computation time of at least a 20% factor, when compared to traditional FFT algorithms and, at the same time, decreases the memory utilization up to a 20% factor over state of the art pruning algorithms.

关键词： Memory management Complexity theory OFDM Communication systems Reduced instruction set computing Embedded systems Algorithm design and analysis

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ELM-based hyperspectral imagery processor for onboard real-time classification

ELM-based hyperspectral imagery processor for onboard real-t...

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conference on design and architectures for signal and image processing

作者： Koldo Basterretxea Unai Martinez-Corral Raúl Finker Inés del Campo Dept. Electronics Technology University of the Basque Country (UPV/EHU) Bilbao Basque Country Spain Dept. Electricity and Electronics University of the Basque Country (UPV/EHU) Leioa Basque Country Spain

ISBN: (纸本)9781509030859

Hyperspectral imagery is being widely used for accurate object detection and terrain feature classification. Modern imaging spectrometers produce huge amounts of data that are compressed onboard and downloaded to ground stations to be processed. Increasing spectral resolution and data acquisition rates demand more efficient compression techniques to meet downlink bandwidth restrictions. A different approach to reducing data-transfer bottlenecks consists of processing hyperspectral imagery information onboard. Real-time onboard processing would, at the same time, broaden the scope of missions that spacecrafts and aircrafts carrying hyperspectral cameras could fulfill by providing them with immediate decision-making capacity in critical circumstances. This paper investigates the use of Extreme Learning Machines (ELMs) for the classification of high dimensional data, and how specialized hardware and application-specific processor design can help to produce high performance, lightweight, and reduced power consumption systems for onboard hyperspectral imagery processing.

关键词： Hyperspectral imaging Training image classification Field programmable gate arrays Real-time systems Neurons

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Demo: Efficient delay and apodization for on-FPGA 3D ultrasound

Demo: Efficient delay and apodization for on-FPGA 3D ultraso...

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conference on design and architectures for signal and image processing

作者： A. C. Yüzügüler W. Simon A. Ibrahim F. Angiolini M. Arditi J.-P. Thiran G. De Micheli Fédérale de Ecole Polytechnique Lausanne (EPFL) Switzerland

ISBN: (纸本)9781509030859

In medical diagnosis, ultrasound (US) imaging is one of the most common, safe, and powerful techniques. Volumetric (3D) US is potentially very attractive, compared to 2D US, because it might enable telesonography - decoupling the local image acquisition, by an untrained person, and the diagnosis, by the trained sonographer, who can be remote. Unfortunately, current 3D systems are hospital-oriented, bulky and expensive, and they cannot be available in emergency operations or rural areas. This motivates us to develop a portable US platform with cheap, battery-operated, more efficient electronics.

关键词： Delays Three-dimensional displays Field programmable gate arrays Computer architecture Transducers image reconstruction Ultrasonic imaging

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An in-band reconfigurable network node based on a heterogeneous platform

An in-band reconfigurable network node based on a heterogene...

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conference on design and architectures for signal and image processing

作者： E. Markert E. Billich C. Tischendorf U. Proß T. Leibelt U. Heinkel J. Knäblein A. Schneider Chair Circuit and Systems Design Chemnitz University of Technology Germany Technische Universitat Chemnitz Chemnitz Sachsen DE CoreMountains GmbH Chemnitz Germany BlueWonder Communications GmbH Dresden CoreMountains GmbH Chemnitz Alcatel-Lucent Nuremberg Germany

This paper describes the implementation of a heterogeneous network node as a reconfigurable application based on embedded ASIC technology. The key points of the paper are the distribution of the reconfiguration data in-band over the network and the in-service-reconfiguration of the network node itself. The node consists of a static ASIC part and three reconfigurable various-grained FPGA-like areas included in one chip. The overall goal is to implement a system that can monitor an Ethernet data stream, extracts configuration data marked by the EtherType field in the Ethernet header and updates its functionality during operation time.

关键词： Field programmable gate arrays Ethernet networks System-on-a-chip Random access memory Protocols Hardware

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