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conference on design and architectures for signal and image processing

作者： Ab Al-Hadi Ab Rahman Hossam Amer Anatoly Prihozhy Christophe Lucarz Marco Mattavelli SCI-STI-MM École Polytechnique Fédérale de Lausanne Lausanne Switzerland

signal processing designs are becoming increasingly complex with demands for more advanced algorithms. designers are now seeking high-level tools and methodology to help manage complexity and increase productivity. Recently, CAL dataflow language has been specified which is capable of synthesizing dataflow description into RTL codes for hardware implementation, and based on several case studies, have shown promising results. However, no work has been done on global network analysis, which could increase the optimization space. In this paper, we introduce methodologies to analyze and optimize CAL programs by determining which actions should be parallelized, pipelined, or refactored for the highest throughput gain, and then providing tools and techniques to achieve this using minimum resource. As a case study on the RVC MPEG-4 SP Intra decoder for implementation on Virtex-5 FPGA, experimental results confirmed our analysis with throughput gain of up to 3.5x using relatively-minor additional slice compared to the reference design.

关键词： Pipeline processing Decoding Optimization Hardware Throughput Clocks Registers

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Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation

Automated generation of an efficient MPEG-4 Reconfigurable V...

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conference on design and architectures for signal and image processing

作者： Ruirui Gu Jonathan Piat Mickael Raulet Jorn W. Janneck Shuvra S. Bhattacharyya Department of Electrical and Computer Engineering University of Maryland College Park MD USA IETR Laboratory UMR CNRS 6164 Image and Remote Sensing Group Rennes France

This paper proposes an automatic design flow from user-friendly design to efficient implementation of video processing systems. This design flow starts with the use of coarse-grain dataflow representations based on the CAL language, which is a complete language for dataflow programming of embedded systems. Our approach integrates previously developed techniques for detecting synchronous dataflow (SDF) regions within larger CAL networks, and exploiting the static structure of such regions using analysis tools in The Dataflow interchange format Package (TDP). Using a new XML format that we have developed to exchange dataflow information between different dataflow tools, we explore systematic implementation of signal processing systems using CAL, SDF-like region detection, TDP-based static scheduling, and CAL-to-C (CAL2C) translation. Our approach, which is a novel integration of three complementary dataflow tools - the CAL parser, TDP, and CAL2C - is demonstrated on an MPEG Reconfigurable Video Coding (RVC) decoder.

关键词： Transform coding XML Video coding Decoding Digital signal processing Computational modeling Libraries

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RICO: A low power repetitive iteration CORDIC for DSP applications in portable devices

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JOURNAL OF SYSTEMS ARCHITECTURE 2016年 70卷 82-92页

作者： Nawandar, Neha K. Garg, Bharat Sharma, G. K. ABV Indian Inst Informat Technol & Management Gwalior Morena Link RdRoom 112Acad Block Gwalior 474015 India

COordinate Rotation Digital Computer (CORDIC) is a unit that is widely used in the applications such as scientific calculators, signal/image processing, communication systems, robotics, 3-D graphics etc. exhibits huge computations and requires large power. This paper presents an approximate low power Repetitive Iteration CORDIC (RICO) architecture that calculates sine/cosine values very efficiently. In the proposed RICO, number of iterations are fixed and a specific iteration is repeated to reduce the implementation complexity. An additional comparator based logic that evaluates direction of micro-rotation within RICO reduces the data dependency between each iterations. The efficiency of the proposed RICO is evaluated in Discrete Cosine Transform (DCT) by implementing DCT using only three RICO units. Post-synthesis simulation results show that the proposed RICO achieves area and power savings of 37.19% and 94.05% respectively over the Conventional CORDIC at the cost of 29.39% increase in latency. (C) 2016 Published by Elsevier B.V.

关键词： CORDIC Rotation (R-p) Scaling factor (k) Discrete Cosine Transform (DCT) Approximate design

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Real-time correlation for locating systems utilizing heterogeneous computing architectures

Real-time correlation for locating systems utilizing heterog...

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conference on design and architectures for signal and image processing

作者： Marc Reichenbach Max Kasparek Mohammad Alawieh Konrad Häublein Dietmar Fey Department Computer Science Friedrich-Alexander-Universitat Erlangen-Niirnberg (FAU) Fraunhofer Institut fur integrierte Schaltungen (IIS)

The usage of locating systems in sports (e.g. soccer) elevates match and training analysis to a new level. By tracking players and balls during matches or training, the performance of players can be analyzed, the training can be adapted and new strategies can be developed. The radio-based RedFIR system equips players and the ball with miniaturized transmitters, while antennas distributed around the playing field receive the transmitted radio signals. A cluster computer processes these signals to determine the exact positions based on the signals' Time Of Arrival (TOA) at the back end. While such a system works well, it is neither scalable nor inexpensive due to the required computing cluster. Also the relatively high power consumption of the GPU-based cluster is suboptimal. Moreover, high speed interconnects between the antennas and the cluster computers introduce additional costs and increase the installation effort. However, a significant portion of the computing performance is not required for the synthesis of the received data, but for the calculation of the unique TOA values of every receiver line. Therefore, in this paper we propose a smart sensor approach: By integrating some intelligence into the antenna (smart antenna), each antenna can correlate the received signal independently of the remaining system and only TOA values are send to the backend. While the idea is quite simple, the question of a well suited computer architecture to fulfill this task inside the smart antenna is more complex. Therefore, we are evaluating embedded architectures, such as FPGAs, ARM cores as well as a many core CPU (Epiphany) for this approach. Thereby, we are able to achieve 50.000 correlations per second in each smart antenna. As a result, the backend becomes lightweight, cheaper interconnects through data reduction are required and the system becomes more scalable, since most processing power is already included in the antenna.

关键词： Computer architecture Correlation Antennas Field programmable gate arrays Intelligent sensors Receivers Hardware

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Memory management in embedded vision systems: Optimization problems and solution methods

Memory management in embedded vision systems: Optimization p...

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conference on design and architectures for signal and image processing

作者： Khadija Hadj Salem Yann Kieffer Stéphane Mancini 50 rue Barthélémy de Laffemas BP 54 LCIS Laboratory Valence France 46 avenue Félix Viallet TIMA Laboratory Grenoble France

ISBN: (纸本)9781509030859

Embedded vision systems design faces a memory-wall kind of challenge: images are big, and therefore memories containing them have high latency; and still, high performance is desired. For the case of non-linear processings, Mancini and Rousseau (Proc. DATE 2012) have designed a software generator of adhoc memory hierarchies, called Memory Management Optimization (MMOpt). While the performance of the generated circuits is very good, design-time decisions have to be made regarding their operation in order to handle finely the compromise between the usual metrics of design area, energy consumption, and performance. This study tackles the optimization challenge set by the design of the operational behavior of the memory hierarchy generated by MMOpt. After a precise formulation as a 3-objective optimization problem is given, two algorithms are proposed, and their performance is analyzed on real-world processings against the previously proposed algorithms. The results show a reduction of the amount of transferred data by 17% on average, and of the computing times by 11.7%, for the same design area.

关键词： Prefetching Optimization Kernel Memory management Algorithm design and analysis Schedules Machine vision

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A hybrid dual-core Reconfigurable Processor for EBCOT tier-1 encoder in JPEG2000 on next generation of digital cameras

A hybrid dual-core Reconfigurable Processor for EBCOT tier-1...

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conference on design and architectures for signal and image processing

作者： Xin Zhao Ahmet T. Erdogan Tughrul Arslan School of Engineering University of Edinburgh UK

In this paper, we present a JPEG2000 EBCOT tier-1 encoder based on a hybrid dual-core processor composed of a coarse-grained Dynamically Reconfigurable Processor (DRP) and an ARM core targeting next generation of cameras. The complete EBCOT tier-1 encoder is partitioned into two tasks and mapped onto the two cores respectively according to different potentials of the two processors. A Partial Parallel Architecture (PPA) for the Context Modeling (CM) is employed which can be easily tailored for DRP implementation for higher performance. The Arithmetic Encoder (AE) has been optimized as well, with a shared Dual-Port RAM (DPRAM) acting as the communication intermediate between the two cores. For the entire application, the two tasks can be pipelined via the global DPRAM for better performance. Simulation results show that the resulting architecture provides throughput reaching up to 40fps for a 256×256 8-bit grayscale standard Lena test image and shows its advantage compared with some DSP&VLIW applications. In addition, this hybrid processor also shows its high potential for implementing the complete JPEG2000 encoder on it targeting next generation of camera applications.

关键词： Encoding Transform coding Computer architecture Throughput Digital signal processing Kernel Pipelines

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An efficient parallel motion estimation algorithm and X264 parallelization in CUDA

An efficient parallel motion estimation algorithm and X264 p...

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conference on design and architectures for signal and image processing

作者： Youngsub Ko Youngmin Yi Soonhoi Ha School of EECS Seoul National University Seoul South Korea School of ECE University of Seoul Seoul South Korea

H.264/AVC video encoders have been widely used for its high coding efficiency. Since the computational demand proportional to the frame resolution is constantly increasing, it has been of great interest to accelerate H.264/AVC by parallel processing. Recently, graphics processing units (GPUs) have emerged as a viable target for accelerating general purpose applications by exploiting fine-grain data parallelisms. Despite extensive research effort to use GPUs to accelerate the H.264/AVC algorithm, it has not been successful to achieve any speed-up over the x264 algorithm that is known as the fastest CPU implementation because of significant communication overhead between the host CPU and the GPU and intra-frame dependency in the algorithm. In this paper, we propose a novel motion estimation (ME) algorithm tailored for NVIDIA GPU implementation. It is accompanied by a novel pipelining technique, called sub-frame ME processing, to effectively hide the communication overhead between the host CPU and the GPU. The proposed H.264 encoder achieves more than 20% speed-up compared with x264.

关键词： Graphics processing unit Encoding Instruction sets Parallel processing Vectors Algorithm design and analysis Kernel

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A Simplified design Approach for Efficient Computation of DCT 5

A Simplified Design Approach for Efficient Computation of DC...

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2015 Fifth International conference on Communication Systems and Network Technologies (CSNT)

作者： Muchahary, Deboraj Mondal, Abir J. Parmar, Rajesh Singh Borah, Amlan Deep Majumder, Alak NIT Arunachal Pradesh Dept Comp Sci & Engn Yupia India NIT Arunachal Pradesh Dept Elect & Commun Yupia India

ISBN: (纸本)9781479917976

Discrete cosine transform (DCT) is the most widely used transformation technique in the field of signal processing particularly in the areas of image data. This paper addresses the design of parallel architectures for computing DCT using CORDIC. It concentrates on indirect methods, which avoids decomposition of direct DCT equation. In this paper, CORDIC methodology has been used to simplify the traditional indirect techniques for the computation of DCT. The proposed methodology is CORDIC friendly and maintains a regular structure, thereby reducing computational complexity. DCTs are used extensively in the area of digital processing for the purpose of pattern recognition. So the efficient computation of DCT maintaining a transparent design flow is highly solicited.

关键词： RADIX FFT DFT CORDIC DCT

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A new single-error correction scheme based on self-diagnosis residue number arithmetic

A new single-error correction scheme based on self-diagnosis...

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conference on design and architectures for signal and image processing

作者： Yangyang Tang Boutillon, Emmanuel Jego, Christophe Jezequel, Michel Universit&#x00E9 Bretagne Sud UMR CNRS 3192 Lab-STICC Universit&#x00E9 Europ&#x00E9 enne de Bretagne BP 92116 56321 Lorient Cedex France

ISBN: (纸本)9781424487349

With the rapid size shrinking in electronic devices, radiation-induced soft-error has emerged as a major concern to the current circuit manufacturing. In this paper, we present a new error correction scheme based on the residue number arithmetic to cope with the single soft-error issue. The proposed technique called bidirectional redundant residue number system requires the redundant moduli to satisfy some constraints to achieve fast error correction. In this system, both the iterations for decoding the valid number and the error-correcting table that contains all combinations of erroneous digit, are not necessary. The detection and the diagnosis are simultaneously performed in plural parallel consistent-checking that has the capability of locating the corrupt digit. Finally, efficient pipeline architecture for the self-diagnosis decoder is detailed.

关键词： Single event transient fault tolerant hardware design residue number system self-diagnosis arithmetic residue number systems computer hardware design Fault tolerance error correction Single event transients arithmetic

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Fuzzy logic modeling for objective image quality assessment

Fuzzy logic modeling for objective image quality assessment

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conference on design and architectures for signal and image processing

作者： Ghislain Takam Tchendjou Rshdee Alhakim Emmanuel Simeu CNRS Université Grenoble Alpes Grenoble France

ISBN: (纸本)9781509030859

This paper presents a novel methodology of objective image quality assessment (IQA) based on Fuzzy Logic (FL) method. The main purpose is to automatically assess the quality of image in agreement with human visual perception. The used attributes (quality metrics) and evaluation criteria (human rating mean opinion score MOS) are extracted from image quality database TID2013. The fuzzy model design starts by selecting the most independent attributes, by applying Pearson's correlation approach and seeking the most correlated metrics with the corresponding MOS. Then, Adaptive Neuro-Fuzzy Inference System (ANFIS) is applied in order to construct an objective fuzzy model able to efficiently predict the image quality correlated with the subjective MOS. In this paper, different fuzzy models are produced by modifying certain ANFIS configurations. After that, we select the appropriate ANFIS model that provides high prediction accuracy and stability with taking into account its implementation complexity. The overall architecture of the selected FL model consists of four input metrics, two bell-shaped membership functions associated to each input metric, two fuzzy if-then rules, two linear combination equations and one output which gives the image adequate quality score. Finally the performance of the proposed fuzzy model is compared with other IQA models produced by different machine learning methods, the simulation results demonstrate that the fuzzy logic model has a high stable behavior with the best agreement with human visual perception.

关键词： Fuzzy logic Measurement image quality Mathematical model Predictive models Correlation Training

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