Field Programmable Gate Arrays (FPGAs) have been extensively used in accelerating applications in many digital domains, examples include image and signalprocessing. These applications have been abundantly tested in h...
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ISBN:
(纸本)9781467365413
Field Programmable Gate Arrays (FPGAs) have been extensively used in accelerating applications in many digital domains, examples include image and signalprocessing. These applications have been abundantly tested in high level languages like C, C++ and Matlab programming. Many standard libraries exist for imageprocessing applications like OpenCV for end to end solutions. Applications centered around these libraries when implemented on embedded platforms like ARM or Power PC consumes considerable amount of processing time. In the last decade, these applications have been heavily tested on FPGAs as hardware (HW) for higher performance gain. Many optimizations and architectures have been proposed in this area examples are parallelism extraction, operation scheduling, pipelining, loop unrolling etc.. In this paper, we present a combination of optimizations and architecture for imageprocessing applications on FPGAs. For software (SW), LLVM compiler has been used for applying optimizations and finding SW execution time on the Ubuntu machine. For HW generation and optimization, Vivado-HLS has been used and tested with four filters on Virtex-5 ML507 kit. The result shows the performance comparison of four C programs as software/hardware with respect to time and resource consumption.
作者：
Akanksha KantShobha SharmaVSLI Design
Indira Gandhi Delhi Technical University For Women New-Delhi India ECE
Indira Gandhi Delhi Technical University For Women New-Delhi India
Rapidly growing technology has raised demands for fast and efficient real time digital signalprocessing applications. Multiplication is one of the primary arithmetic operations every application demands. A large numb...
Rapidly growing technology has raised demands for fast and efficient real time digital signalprocessing applications. Multiplication is one of the primary arithmetic operations every application demands. A large number of multiplier designs have been developed to enhance their speed. Active research over decades has lead to the emergence of Vedic Multipliers as one of the fastest and low power multiplier over traditional array and booth multipliers. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. A large number of them have been proposed using Urdhava Tiryakbhyam sutra rendering them most efficient in terms of speed. The objective of this paper is to encapsulate an array of applications of Vedic Multiplier in the vast domain of imageprocessing and Digital signalprocessing, particularly the different modifications of existing Vedic Multiplier architectures enhancing their speed and performance parameters.
Generally, 2-D DCT/IDCT (Two dimensional discrete cosine transform and its inverse) are widely used in many imageprocessing systems. In this paper, efficient architectures are proposed. These architectures have paral...
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ISBN:
(纸本)9781479980826
Generally, 2-D DCT/IDCT (Two dimensional discrete cosine transform and its inverse) are widely used in many imageprocessing systems. In this paper, efficient architectures are proposed. These architectures have parallel and pipelined structures which are used to implement 8×8 DCT/IDCT processors. These processors involve two 8-point DCT/IDCT processors along with a dual-bank of SRAM (128 words) and a coefficient ROM (6 words), a control unit and two multiplexers. Here, CORDIC arithmetic is used to design the kernel arithmetic unit (AU). The proposed architectures for 2-D DCT/IDCT not only reduce the power consumption but also simplify the hardware with a very high performance.
Due to the power limitation and the small size condition of the wireless capsule endoscopy, therefore the principal defiance is to reduce the area and the power consumption. The aim is to preserve acceptable image rec...
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Due to the power limitation and the small size condition of the wireless capsule endoscopy, therefore the principal defiance is to reduce the area and the power consumption. The aim is to preserve acceptable image reconstruction and coding. In this paper, we present a Low complexity and efficient architecture of 1D-DCT based Cordic-Loeffler technique for wireless capsule endoscopy. Our improvement over the original algorithm is performed in CORDIC part. This brings us to reduce the number of addition operations from 18 to 10. As a result, the number of addition is reduced from 38 to 30 operations in the main algorithm. Also, to more ameliorate our results, we used Modified Carry look Ahead adder (MCLA) and Carry Save Adder (CSA) adder which are characterized by low power and high speed compared to classical Carry Look Ahead adder (CLA). Our aim is to provide an optimized architecture in terms of area and power consumption. The proposed design has been implemented on FPGA. Compared to other architectures, the proposed architecture has not only reduced the computation complexity, but also the area and the power consumption. It should be noted that the proposed DCT architecture is very suitable for low-power and high-quality codecs, especially for battery-based systems.
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