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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是21-30 订阅

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Hardware-software abandoned object detection vision system in heterogeneous Zynq device

Hardware-software abandoned object detection vision system i...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Kryjak, Tomasz Skirzynski, Artur Gorgon, Marek AGH Univ Sci & Technol Krakow Poland

ISBN: (纸本)9781538635346

In this paper a hardware-software abandoned object detection vision system implemented in the Zynq SoC (System on Chip) device is presented. First, the solution was implemented in C++ and run as a bare metal application on the ARM processor core of the Zynq (using floating and fixed-point computations). For the target video stream 1280 x 720 @ 50 fps (74.25 MHz pixel clock) it reached only 2 fps. Therefore, to speed-up the application, it was decided to move some of the image processing and analysis operations to the programmable logic. This allowed to obtain real-time image processing i.e. 50 fps, with power consumption of less than 4W.

关键词： Object detection Streaming media C++ languages Real-time systems Machine vision Algorithm design and analysis Labeling

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An Efficient Framework for design and Assessment of Arithmetic Operators with Reduced-Precision Redundancy

An Efficient Framework for Design and Assessment of Arithmet...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Wali, Imran Casseau, Emmanuel Tisserand, Arnaud Univ Rennes 1 IRISA Rennes France CNRS UMR6285 Lab STICC Lorient France

ISBN: (纸本)9781538635346

For arithmetic circuits, Reduced-Precision Redundancy (RPR) is considered to be a viable alternative to Triple Modular Redundancy (TMR), as it offers significant power reduction. However, efficient implementation and assessment of hardware arithmetic operators with RPR is still a challenge. In this work we propose a lightweight RPR design methodology that exploits the capabilities of modern synthesis and simulation tools to simplify the design and verification of robust arithmetic operators. To demonstrate the effectiveness of the proposed framework we apply it to implement and compare two commonly used RPR schemes. Our experimental results show that the proposed framework simplifies the design and provides robustness indicators with a maximum coefficient of variation of 14.7% with a 3x experimentation speed-up at a cost of 25% computational effort compared to an exhaustive approach.

关键词： Robustness Circuit faults Power demand Error analysis Redundancy Tools

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Demo: Overlay architectures For Heterogeneous FPGA Cluster Management

Demo: Overlay Architectures For Heterogeneous FPGA Cluster M...

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conference on design and architectures for signal and image processing (dasip)

作者： Bollengier, Theotime Najem, Mohamad Le Lann, Jean-Christophe Lagadec, Loic B Com Brest France ENSTA Bretagne Lab STICC MOCS Brest France

ISBN: (纸本)9791092279153

Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features independent from the host FPGA. We designed a fine-grained overlay implementing novel features easing the management of such architectures in a cluster of heterogeneous COTS FPGAs. This demonstration shows the use of this overlay in an FPGA cluster, performing a hardware application live migration between two nodes of a cluster. It also illustrates fault tolerance of the cluster.

关键词： Field programmable gate arrays (FPGA)

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design Flow for Portable Dataflow Programming of Heterogeneous Platforms 12

Design Flow for Portable Dataflow Programming of Heterogeneo...

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12th conference on design and architectures for signal and image processing (dasip)

作者： Boutellier, Jani Lunnikivi, Henri Tampere Univ Technol Lab Pervas Comp Tampere Finland

ISBN: (纸本)9781538682371

The processing platforms of contemporary mobile devices are commonly built around System-on-Chip (SoC) solutions that contain general purpose processor cores (GPPs), digital signal processors, accelerator circuits, and possibly a graphics processing unit (GPU) as processing resources. Software design for such SoCs can be very time-consuming, as the various processing resource types (e.g. GPPs and GPUs) conventionally require different languages to be programmed. For example, GPUs are programmed via CUDA or OpenCL, whereas GPPs are commonly programmed in C++. As a consequence, code that has originally been written for one processing resource, cannot necessarily be executed on a different processing resource type. This paper presents a novel design flow that addresses this code portability challenge. On a high level the application is described using a dataflow graph, whereas the detailed functionality of application components is written in Halide, a performance portable language that provides code generation for OpenCL, CUDA, HVX DSP, ARM and x86 targets. The proposed design flow is built around PRUNE, a recent dataflow programming framework. The functionality of the design flow is presented with three case study applications, and the measurements show an average speedup of 9.3x over single-core C code when the proposed design flow is used.

关键词： dataflow programming parallel processing digital signal processing

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Video++, a modern image and video processing C++ framework 8

Video++, a modern image and video processing C++ framework

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2014 8th conference on design and architectures for signal and image processing, dasip 2014

作者： Garrigues, Matthieu Manzanera, Antoine ENSTA-ParisTech 828 Boulevard des Maréchaux Palaiseau Cedex91762 France

ISBN: (纸本)9791092279054

We present in this paper Video++, a new framework targeting image and video applications running on multi-core processors. While offering a high expressive power, we show that it generates code running up to 32 times faster than the naive equivalents. Taking advantage of the new C++11/C++14 features, tools, we propose simple abstractions matching the performance of hand optimized code. This paper gives an overview of the library and demonstrates its efficiency with some benchmarks. © 2014 European Electronic Chips & Systems design Initiative - ECSI.

关键词： Video signal processing

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Real-time implementation of contextual image processing operations for 4K video stream in Zynq UltraScale plus MPSoC 12

Real-time implementation of contextual image processing oper...

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12th conference on design and architectures for signal and image processing (dasip)

作者： Kowalczyk, Marcin Przewlocka, Dominika Kryjak, Tomasz AGH Univ Sci & Technol Krakow Krakow Poland

ISBN: (纸本)9781538682371

In this paper hardware implementation of selected contextual based image pre-processing modules for a 3840x2160 @60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. The following operations are considered: simple averaging (box filter), Gaussian filter, edge detection using the Sobel and Canny methods, median filter and morphological erosion and dilation operations. The scheme for implementing contextual based operations for a video stream in the format of 2 and 4 pixels per clock and challenges related to the pipelined implementation of processing such data are described. Also the use of logic resources and energy efficiency of modules described in the Verilog hardware description language and using the High Level Synthesis tools (Vivado HLS, SDSoC and xfOpenCV library) are compared. All designed modules support real-time processing of a 4K@60 fps video stream.

关键词： FPGA Zynq SoC image pre-processing contextual based filtering real-time processing Sobel Canny Vivado HLS SDSoC xfOpenCV

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Real-time implementation of adaptive correlation filter tracking for 4K video stream in Zynq UltraScale plus MPSoC 13

Real-time implementation of adaptive correlation filter trac...

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conference on design and architectures for signal and image processing (dasip)

作者： Kowalczyk, Marcin Przewlocka, Dominika Kryjak, Tomasz AGH Univ Sci & Technol Krakow Poland

ISBN: (纸本)9781728140742

In this paper a hardware-software implementation of adaptive correlation filter tracking for a 3840 x 2160 @ 60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. Correlation filters gained popularity in recent years because of their efficiency and good results in the VOT (Visual Object Tracking) challenge. An implementation of the MOSSE (Minimum Output Sum of Squared Error) algorithm is presented. It utilizes 2-dimensional FFT for computing correlation and updates filter coefficients in every frame. The initial filter coefficients are computed on the ARM processor in the PS (processing System), while all other operations are preformed in PL (Programmable Logic). The presented architecture was described with the use of Verilog hardware description language.

关键词： FPGA Zynq SoC image processing object tracking real-time processing correlation filter MOSSE

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image Tiling for Embedded Applications with Non-Linear Constraints

Image Tiling for Embedded Applications with Non-Linear Const...

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conference on design and architectures for signal & image processing

作者： Schwambach, Vitor Cleyet-Merle, Sebastien Issard, Alain Mancini, Stephane Univ Grenoble Alpes TIMA F-38031 Grenoble France CNRS TIMA F-38031 Grenoble France STMicroelectronics Grenoble France

ISBN: (纸本)9791092279115

Tiling is a key aspect of the design of embedded image processing applications, due to local memory constraints. To maximize system performance, the designer must select a suitable tile size that balances data transfers and computation. In this work, we present a method for optimal 2D image tile sizing using constraint programming. Unlike previous methods, ours accurately models DMA data transfer times and parallel scheduling overheads with non-linear constraints. Our experiments with a binomial filter demonstrate that we can compute the optimal tiling dimensions that minimize the execution time for different image sizes and internal memory constraints. This technique provides invaluable information for both application developers and system architects that can quickly explore design trade-offs.

关键词： Modeling design Optimization image processing Embedded Software

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BM3D image Denoising Using Heterogeneous Computing Platforms

BM3D Image Denoising Using Heterogeneous Computing Platforms

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conference on design and architectures for signal & image processing

作者： Sarjanoja, Sampsa Boutellier, Jani Hannuksela, Jari Univ Oulu Ctr Machine Vis Res Oulu Finland

ISBN: (纸本)9791092279115

Noise reduction is often performed at an early stage of the image processing path. In order to keep the processing delays small in different computing platforms, it is important that the noise reduction is performed swiftly. In this paper, the block-matching and three-dimensional filtering (BM3D) denoising algorithm is implemented on heterogeneous computing platforms using OpenCL and CUDA frameworks. To our knowledge, these implementations are the first successful open source attempts to use GPU computation for BM3D denoising. The presented GPU implementations are up to 7.5 times faster than their respective CPU implementations. At the same time, the experiments illustrate general design challenges in using massively parallel processing platforms for the calculation of complex imaging algorithms.

关键词： image denoising Parallel processing Parallel algorithms Mobile computing

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Hardware-based architecture for asymmetric numeral systems entropy decoder

Hardware-based architecture for asymmetric numeral systems e...

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2017 conference on design and architectures for signal and image processing, dasip 2017

作者： Najmabadi, Seyyed Mahdi Tungal, Harsimran Singh Tran, Trung-Hieu Simon, Sven Department of Parallel Systems University of Stuttgart Stuttgart70569 Germany

ISBN: (纸本)9781538635346

In this paper, two novel hardware architectures based on tabled asymmetric numeral systems decoding algorithm are proposed. In the proposed architectures the decoding throughput is highly dependent on the how much the data is compressed at encoding time. The synthesis results presented here show that the throughput of the parallel architecture can reach up 200 MB/s. The benchmarks show that the parallel architecture that runs on Xilinx Kintex FPGA provides higher throughout in comparison with the same algorithm running on Core i3 CPU. © 2017 IEEE.

关键词： Parallel architectures

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