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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是31-40 订阅

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GPU based Quarter Spectral Correlation Density Function 12

GPU based Quarter Spectral Correlation Density Function

引用

12th conference on design and architectures for signal and image processing (dasip)

作者： Marshall, Scott Vanhoy, Garrett Akoglu, Ali Bose, Tamal Ryu, Bo Uni Arizona Dept Elect & Comp Engn Tucson AZ 85719 USA EpiSys Sci Inc Poway CA USA

ISBN: (纸本)9781538682371

In this study we investigate the parallelization of a key feature extraction method called spectral correlation density (SCD) function, which is used in signal classification systems particularly under low signal-to-noise ratio conditions for classifying numerous signals. In order to reduce the computation complexity of the SCD function, we introduce a method called Quarter SCD (QSCD) that allows extracting features of a given signal by processing only quarter of the input signal data. We then parallelize the QSCD by targeting general purpose graphics processing unit (GPU) through architecture specific optimization strategies. We present experimental evaluations on identifying the parallelization configuration for maximizing the efficiency of the program architecture in utilizing the threading power of the GPU architecture. We show that algorithmic and architecture specific optimization strategies result with improving the throughput of the state of the art GPU based Full SCD from 120 signals/second to 2719 signals/second.

关键词： GPGPU signal classification spectral correlation density

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designing processors using MAsS, a modular and lightweight instruction-level exploration tool

Designing processors using MAsS, a modular and lightweight i...

引用

2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Texier, Matthieu Piriou, Erwan Thevenin, Mathieu David, Raphaël CEA LIST Embedded Computing Laboratory - PC94 F91191 Gif sur Yvette France

ISBN: (纸本)9781457706196

As application complexity increases, the design of efficient computing architectures able to cope with embedded constraints requires a fine algorithm analysis. This paper proposes an original approach based on Modular Assembly Simulator (MAsS) tool that allows design Space Exploration (DSE) for programmable processors. The originality of the method resides in its capacity to generate operator level simulators allowing a quick code analysis from real data sets. This paper also presents two successfully designed architectures using MAsS. © 2011 IEEE.

关键词： Integrated circuit design

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XMSIM: A tool for early memory hierarchy evaluation

XMSIM: A tool for early memory hierarchy evaluation

引用

6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Dimitroulakos, Grigoris Lioris, Theodoros Lezos, Christakis Masselos, Konstantinos University of Peloponnese Department of Computer Science and Technology Terma Karaiskaki 22100 Tripoli Greece

In this demonstration we present the usage of XMSIM, a tool for memory hierarchy evaluation of multimedia applications. The input is a high level C code application description and a memory hierarchy specification and... 详细信息

ISBN: (纸本)9782953998726

关键词： Computer aided design

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Foreground detection and image segmentation in a flexible ASVP platform for FPGAs

Foreground detection and image segmentation in a flexible AS...

引用

6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Bartosinski, Roman Danek, Martin Sykora, Jaroslav Kohout, Lukas Honzik, Petr of the ASCR v.v.i. Pod Vodarenskou vezi 4 Praha Czech Republic CIP Plus S.r.o. Milinska 130 Pribram Czech Republic

ISBN: (纸本)9782953998726

This demonstration shows an early prototype of low-level image processing to be used in an embedded smart camera, that is foreground detection and image segmentation. The example uses camera with resolution 640×480 pixels for input images processed at 100MHz in the FPGA. The input can be easily extended to higher resolutions. The processed output is displayed on LCD screen. © 2012 ECSI.

关键词： Field programmable gate arrays (FPGA)

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A framework for the design of reconfigurable fault tolerant architectures

A framework for the design of reconfigurable fault tolerant ...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Pham, Hung Manh Pillement, Sébastien Pasquier, Olivier Le Nours, Sébastien University of Rennes I IRISA 6 rue de Kerampont 22302 Lannion France IREENA - Polytech Nantes Rue Christian Pauc 44306 Nantes Cedex 3 France

ISBN: (纸本)9781457706196

The rapid evolutions in reconfigurable electronic products design permit to handle more and more complex applications. New fields of investigations (i.e. automotive, aerospatial, banking,...) are interesting but require a high level of dependability. This paper proposes a framework to design reconfig-urable architecture supporting fault-tolerance mitigation scheme. The proposed framework allows simulation, validation of mitigation operations, but also to size architecture resources. The implementation of a fault-tolerant reconfigurable platform permits to validate the proposed model and the effectiveness of the framework. This implementation shows the potential of dynamically reconfigurable architectures for supporting fault-tolerance in embedded systems. © 2011 IEEE.

关键词： Fault tolerance

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High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA

High level design of adaptive distributed controller for par...

引用

2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Cherif, Sana Trabelsi, Chiraz Meftali, Samy Dekeyser, Jean-Luc INRIA Lille Nord Europe LIFL USTL 40 avenue Halley 59650 Villeneuve d'Ascq France

ISBN: (纸本)9781457706196

Controlling dynamic and partial reconfigurations becomes one of the most important key issues in modern embedded systems design. In fact, in such systems, the reconfiguration controller can significantly affect the system performances. Indeed, the controller has to handle efficiently three major tasks during runtime: observation (monitoring), taking reconfiguration decisions and notify decisions to the rest of the system in order to realize it. We present in this paper a novel high level approach permitting to model, using MARTE UML profile, modular and flexible distributed controllers for dynamic reconfiguration management. This approach permits components/ models reuse and allows systematic code generation. It consequently makes reconfigurable systems design less tedious and reduces time to market. © 2011 IEEE.

关键词： Controllers

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Power Efficient Dataflow design for a Heterogeneous Smart Camera Architecture

Power Efficient Dataflow Design for a Heterogeneous Smart Ca...

引用

conference on design and architectures for signal and image processing (dasip)

作者： Bhowmik, Deepayan Garcia, Paulo Wallace, Andrew Stewart, Robert Michaelson, Greg Sheffield Hallam Univ Dept Comp Sheffield S1 1WB S Yorkshire England Heriot Watt Univ Sch Engn & Phys Sci Edinburgh EH14 4AS Midlothian Scotland Heriot Watt Univ Math & Comp Sci Edinburgh EH14 4AS Midlothian Scotland

ISBN: (纸本)9781538635346

Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low.

关键词： Field programmable gate arrays image processing Hardware Smart cameras Computer architecture Computational modeling

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Hardware Architecture design and Implementation for FMCW Radar signal processing Algorithm 8

Hardware Architecture Design and Implementation for FMCW Rad...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Eugin, Hyun Lee, Jonghun DGIST ART Adv Radar Technol Lab Robot Res Div Daegu South Korea

ISBN: (纸本)9791092279061

Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target;even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times.

关键词： FMCW radar detection algorithm chirp sequence

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Efficient Architecture for Implementation of Hermite Interpolation on FPGA 12

Efficient Architecture for Implementation of Hermite Interpo...

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12th conference on design and architectures for signal and image processing (dasip)

作者： George, Gibin Chacko Moitra, Abhishek Caculo, Sriyash Prince, A. Amalin BITS Pilani Dept EEE Goa Campus Pilani Goa India

ISBN: (纸本)9781538682371

Interpolation is widely used for a number of applications. For instance, it is used to generate geometric models, path trajectories and various applications of signal processing including data compression. Traditionally, software implementation of interpolation is carried out using a General Purpose Processor (GPP) or Digital signal Processor (DSP). Field Programmable Gate Arrays (FPGAs) however, offer a more customizable and faster solution. This paper presents a hardware accelerator architecture for Hermite Interpolation on FPGA. Cubic Hermite interpolation, specifically Catmull-Rom spline is preferred over other techniques due to ease of computation and local control which makes it an ideal method to implement very low-complexity architecture. A data flow approach has been used as it provides high throughput for intensive data processing. Additionally, the efficiency of computation has been improved by implementing a pipelined architecture. The proposed architecture has been implemented on Xilinx Zynq-7000 AP SoC XC7Z020-CLG484 using the Xilinx Vivado design Suite. Results obtained from fixed point FPGA implementation were found to have high fidelity with floating point MATLAB simulations. Root Mean Squared Error (RMSE) of 1.704x10(-4) and a correlation of 99.84% was obtained.

关键词： Field Programmable Gate Array Interpolation Digital signal processing Hermite Interpolation Catmull-Rom Spline Data Flow Architecture

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The multi-dataflow composer tool: A runtime reconfigurable HDL platform composer

The multi-dataflow composer tool: A runtime reconfigurable H...

引用

2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Palumbo, Francesca Carta, Nicola Raffo, Luigi DIEE - Dept. of Electrical and Electronic Engineering University of Cagliari P.zza D'Armi 09123 Cagliari Italy

ISBN: (纸本)9781457706196

Dataflow Model of Computation (D-MoC) is particularly suitable to close the gap between hardware architects and software developers. Leveraging on the combination of the D-MoC with a coarse-grained reconfigurable approach to hardware design, we propose a tool, the Multi-Dataflow Composer (MDC) tool, able to improve time-to-market of modern complex multi-purpose systems by allowing the derivation of HDL runtime reconfigurable platforms starting from the D-MoC models of the targeted set of applications. MDC tool has proven to provide a considerable on-chip area saving: the 82% of saving has been reached combining of different applications in the image processing domain, adopting a 90 nm CMOS technology. In future the MDC tool, with a very small integration effort, will also be extremely useful to create multi-standard codec platforms for MPEG RVC applications. © 2011 IEEE.

关键词： image processing

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