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检索条件"任意字段=Conference on Design and Architectures for Signal and Image Processing, DASIP 2015"

共 266 条记录，以下是81-90 订阅

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Development of a method for image-based motion estimation of a VTOL-MAV on FPGA

Development of a method for image-based motion estimation of...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Frietsch, N. Pashkovskiy, I. Trommer, G.F. Braun, L. Birk, M. Hübner, M. Becker, J. Karlsruhe Germany Karlsruhe Germany

ISBN: (纸本)9781457706196

In this paper, the development of the vision based motion estimation for a small-scale VTOL-MAV as well as the implementation on FPGA are investigated. Especially in urban environments the GPS signal quality is disturbed by shading and multipath propagation and an augmentation with another sensor is inevitable. The vision system bases on the analysis of the sparse optical flow that is extracted from images taken by the onboard camera. From the extracted point correspondences projective transformations are estimated with a robust parameter estimation algorithm. As the underlying image processing routines are computationally expensive but can be processed in parallel they have been implemented on FPGA. The different parts of the algorithm as well as the implementation are covered in detail. © 2011 IEEE.

关键词： Optical flows

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Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC by means of a Stereo Matching Application 8

Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC ...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Heulot, Julien Menant, Judicael Pelcat, Maxime Nezan, Jean-Francois Morin, Luce Pressigout, Muriel Aridhi, Slaheddine UEB CNRS UMR 6164 INSA Rennes IETR 20 Ave Buttes de Coesmes Rennes France Texas Instruments France Cagnes Sur Mer France

ISBN: (纸本)9791092279061

This demonstration paper presents a multicore Real Time Operating System (RTOS) that schedules a parameterized dataflow Model of Computation (MoC) onto a multicore Digital signal Processor (DSP) at runtime. This RTOS called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPIDER) exploits the Parameterized and Interfaced Synchronous Dataflow (PiSDF) MoC and its features at runtime to identify locally static regions and to optimize their execution onto multicore platforms. The RTOS is used to dispatch a stereo matching algorithm tasks with a varying range of disparities. The platform used for this demonstration is a Texas Instruments Keystone II Multiprocessor System-on-Chip (MPSoC) device composed of 8 DSP cores, 4 ARM cores, a shared memory subsystem, Multicore Navigator and multiple dedicated accelerators.

关键词： Multi-core processors parameterization Runtime data flow Legal Executions Digital signal processing Desmoplakin Gene

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A 3D reconstruction from real-time stereoscopic images using GPU

A 3D reconstruction from real-time stereoscopic images using...

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2013 7th conference on design and architectures for signal and image processing, dasip 2013

作者： Gomez-Balderas, J.E. Houzet, D. Grenoble Image Parole Signal Automatique Lab. GIPSA-Lab UMR5216 Grenoble France

ISBN: (纸本)9791092279016

In this article we propose a new technique to obtain a three-dimensional (3D) reconstruction from stereoscopic images taken by a stereoscopic system in real-time. To parallelize the 3D reconstruction we propose a method that uses a Graphics Processors Unit (GPU) and a disparity map from block matching algorithm (BM). The results obtained permit us to accelerate the images processing time, measured in frames per second (FPS) with respect to the same method using a Central processing Unit (CPU). The advantage of speed using GPU advocates our system for practical applications such as aerial reconnaissance, cartography, robotic navigation and obstacle detection.

关键词： Graphics processing unit

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A Scalable Hardware Architecture for Retinal Blood Vessel Detection in High Resolution Fundus images 8

A Scalable Hardware Architecture for Retinal Blood Vessel De...

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8th conference on design and architectures for signal and image processing (dasip)

作者： Bendaoudi, Hamza Cheriet, Farida Ben Tahar, Houssem Langlois, J. M. Pierre Polytech Montreal Dept Comp & Software Engn Montreal PQ Canada Diagnos Inc Brossard PQ Canada

ISBN: (纸本)9791092279061

Blood vessel detection from high resolution fundus images is a necessary step in several medical applications. Automatic blood vessels detection is a computing intensive task which raises the need for accelerated hardware architectures. In this paper, we propose a scalable hardware architecture for blood vessel detection using a matched filter (MF). The algorithm is made hardware friendly using parallel processing and efficient resources sharing to achieve real-time performances. The paper also introduces a tool for the automatic generation of an HDL description based on the proposed architecture as a template. The tool takes as input the parameters of the filter to deal with the parameter selection problem and to make their choice more flexible. Performances in terms of area utilization and maximum frequency are reported. Several designs were verified and implemented on an FPGA platform. The results show significant improvements over the state of the art implementations, up to a factor of 10x for high resolution fundus images.

关键词： Retinal blood vessels detection Hardware acceleration Scalable hardware architectures

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Flexible VLIW processor based on FPGA for real-time image processing

Flexible VLIW processor based on FPGA for real-time image pr...

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2011 conference on design and architectures for signal and image processing, dasip 2011

作者： Brost, Vincent Meunier, Charles Saptono, Debyo Yang, Fan LE2I-CNRS 5158 Laboratory University of Burgundy 21078 Dijon France

ISBN: (纸本)9781457706196

Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance Very Long Instruction Word (VLIW) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient Instruction Level Parallelism (ILP) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the development cycle, and to use the powerful FPGA resources in order to increase real-time performance. We present a flexible VLIW VHDL processor model with a variable instruction set and a customizable architecture which allow exploiting intrinsic parallelism of a target application using advanced compiler technology and implementing it in an optimal manner on FPGA. Some common algorithms of image processing were tested and validated on an FPGA Virtex-6 based board using the proposed development cycle. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Custom Processor design for Efficient, yet Flexible Lucas-Kanade Optical Flow

Custom Processor Design for Efficient, yet Flexible Lucas-Ka...

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conference on design and architectures for signal and image processing (dasip)

作者： Smets, Sander Goedeme, Toon Verhelst, Marian Katholieke Univ Leuven MICAS ESAT Leuven Belgium Katholieke Univ Leuven PSI EAVISE Campus De Nayer St Katelijne Waver Belgium

ISBN: (纸本)9791092279153

State-of-the-art solutions to optical flow fail to jointly offer high density flow estimation, low power consumption and real time operation, rendering them unsuitable for embedded applications. Joint hardware-software scalability at run-time is crucial to achieve these conflicting requirements in one device. This paper therefore presents a scalable Lucas-Kanade optical flow algorithm, together with a flexible power-optimized processor architecture. The C-programmable processor exploits algorithmic scalability through innovations in its memory structure, memory interface, and datapath optimized for efficient convolutions. Jointly, the scalable flow algorithm and optimized computer vision hardware platform enable applications to on-the-fly trade-off throughput and power consumption in function of flow density and accuracy. The processor chip is synthesized in 40nm CMOS technology and verified on FPGA. The architecture is capable of scaling the frame rate at run-time and processes 16fps of dense optical flow at 640x480 resolution with 15.06 degrees average angular error, while only consuming 24mW.

关键词： Machine vision programmable circuits parallel architectures real time systems low-power electronics

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Reconfigurable Vision processing System for Player Tracking in Indoor Sports

Reconfigurable Vision Processing System for Player Tracking ...

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conference on design and architectures for signal and image processing (dasip)

作者： Ibraheem, Omar W. Irwansyah, Arif Hagemeyer, Jens Porrmann, Mario Rueckert, Ulrich Bielefeld Univ CITEC Cognitron & Sensor Syst Grp Bielefeld Germany

ISBN: (纸本)9781538635346

In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Vision-based player tracking has high computational demands since it requires processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rates. In this paper, we present a reconfigurable system to track the players in indoor sports automatically without user interaction. The proposed system can process live video data streams from multiple cameras as well as offline data from recorded video files. FPGA technology is used to accelerate this player tracking system by implementing the video acquisition, video preprocessing, player segmentation, and team identification & player detection modules in hardware, realizing a real-time system. The teams are identified and the players' positions are detected based on the colors of their jerseys. The detection results are sent from the FPGA to the host-PC where the players are tracked. Our results show that the achieved average player detection rate is up to 95.5%. The proposed system can process live video data using two GigE Vision cameras with a resolution of 1392x1040 pixels and 30 fps for each camera. A speed-up of 20 is achieved compared to an OpenCV-based software implementation on a host-PC equipped with a 2.93 GHz Intel i7 CPU.

关键词： Streaming media Cameras Field programmable gate arrays IP networks image color analysis Games Target tracking

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Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU architectures 12

Energy and Execution Time Comparison of Optical Flow Algorit...

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12th conference on design and architectures for signal and image processing (dasip)

作者： Petreto, Andrea Hennequin, Arthur Koehler, Thomas Romera, Thomas Fargeix, Yohan Gaillard, Boris Bouyer, Manuel Meunier, Quentin L. Lacassagne, Lionel Sorbonne Univ CNRS LIP6 F-75005 Paris France Lheritier Alcen F-95862 Cergy Pontoise France

ISBN: (纸本)9781538682371

This article presents and compares optimized implementations of two optical flow algorithms on several target boards comprising multi-core SIMD processors and GPUs. The two algorithms are Horn-Schunck (HS) and TV-L1, and have been chosen because they are both well-known, and because of their different computational complexity and accuracy. For both algorithms, we have made parallel optimized SIMD implementations, while HS has also been implemented on GPUs. For each algorithm, the comparison between the different versions and target boards is carried out in a two-dimensional fashion: in terms of computing speed-in order to achieve real-time computation-and in terms of energy consumption since we target embedded systems. The results show that for HS, the GPUs are the most efficient in both dimensions, able to process in realtime performances (25 frames per second) up to 8Mpix images for 0.35J per image, against 1.8Mpix images for 0.24J per image on CPU. The results also highlight the impact of optimizations on TV-L1: far slower than HS without optimization, it can almost match its performance after optimization on CPU, and can achieve real-time performances with 0.25J for 1.4Mpix images. We hope these results will help developers design optical flow embedded systems.

关键词： Optimization Graphics processing units Optical imaging Computer architecture Real-time systems Embedded systems Power demand

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Embedded Fluorescence Lifetime Determination for High Throughput Real-Time Droplet Sorting with Microfluidics

Embedded Fluorescence Lifetime Determination for High Throug...

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conference on design and architectures for signal and image processing (dasip)

作者： Lieske, Tobias Uhring, Wilfried Dumas, Norbert Leonard, Jeremie Fey, Dietmar Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Chair Comp Architecture Erlangen Germany Univ Strasbourg ICube Strasbourg France CNRS Paris France Univ Strasbourg IPCMS Strasbourg France

ISBN: (纸本)9781538635346

Time-resolved fluorescence (TRF) analysis is considered to be among the primary research tools in biochemistry and biophysics. One application of this method is the investigation of biomolecular interactions with promising applications for biosensing. For the latter context, time-correlated single photon counting (TCSPC) is the most sensitive, hence preferred implementation of TRF. However, high throughput applications are presently limited by the maximum achievable photon acquisition rate, and even more by the data processing rate. The latter rate is actually limited by the computational complexity to estimate accurately the fluorescence lifetime from TCSPC data. Here we propose a solution that would enable the implementation of TRF detection for fluorescence-activated droplet sorting (FADS), a particularly high throughput, microfluidic-based technology. Most fluorescence lifetime algorithms require a large number of detected photons for an accurate lifetime computation. This paper presents an implementation based on a maximum likelihood estimator (MLE), enabling high precision estimation with a limited number of detected photons, significantly reducing the total measurement time. This speedup rapidly increases the input data rate. As a result, off-the-shelf embedded products cannot handle the data rates produced by current TCSPC units that are used to measure the fluorescence. Therefore, a configurable real-time capable hardware architecture is implemented on a field programmable gate array (FPGA) that can handle the data rates of future TCSPC units, rendering high throughput droplet sorting with microfluidics possible.

关键词： FPGA time-resolved fluorescence fluorescence lifetime microfluidics embedded signal processing

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HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA

HLS-based fast design space exploration of ad hoc hardware a...

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6th Annual conference on design and architectures for signal and image processing, dasip 2012

作者： Corre, Youenn Hoang, Van-Trinh Diguet, Jean-Philippe Heller, Dominique Lagadec, Loic Lab-STICC Université de Bretagne Sud 56100 Lorient France Lab-STICC Université de Bretagne Occidentale 29200 Brest France

ISBN: (纸本)9782953998726

Over the last decade many academic and industrial system synthesis and codesign tools have been proposed to designers. However most of these tools are based on IP Libraries but either these libraries are incomplete or are simply not adapted to the targets and constraints. It means that something important is missing when it comes to real implementations. We address this question in this paper and propose a flexible, fast and practical solution. We use high level synthesis (HLS) to obtain fast estimations of hardware accelerators that can then be embedded within the loop of a larger design space exploration flow. Once some solutions are selected they can be directly reuse to synthesise and produce real IPs. In this paper we present the approach and the tool as a key component of our heterogeneous multiprocessor synthesis framework. © 2012 ECSI.

关键词： High level synthesis

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