检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

201 篇 会议
3 篇 期刊文献

馆藏范围

204 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

178 篇 工学
- 119 篇 电气工程
- 118 篇 机械工程
- 31 篇 材料科学与工程（可...
- 27 篇 计算机科学与技术...
- 14 篇 电子科学与技术（可...
- 11 篇 控制科学与工程
- 11 篇 软件工程
- 5 篇 化学工程与技术
- 4 篇 仪器科学与技术
- 3 篇 光学工程
- 2 篇 冶金工程
- 2 篇 信息与通信工程
- 2 篇 测绘科学与技术
- 2 篇 纺织科学与工程
- 2 篇 环境科学与工程（可...
- 1 篇 力学（可授工学、理...
- 1 篇 轻工技术与工程
- 1 篇 船舶与海洋工程
59 篇 理学
- 50 篇 物理学
- 10 篇 数学
- 3 篇 化学
- 2 篇 系统科学
- 1 篇 海洋科学
19 篇 管理学
- 19 篇 管理科学与工程(可...
- 7 篇 工商管理
- 1 篇 图书情报与档案管...
3 篇 经济学
- 3 篇 应用经济学
2 篇 医学
- 2 篇 临床医学
1 篇 法学
- 1 篇 社会学

主题

29 篇 opc
28 篇 dfm
27 篇 lithography
21 篇 optical proximit...
19 篇 design for manuf...
18 篇 manufacturing
12 篇 photomasks
11 篇 process window
10 篇 resolution enhan...
10 篇 ret
9 篇 design for manuf...
9 篇 semiconducting w...
9 篇 optical lithogra...
8 篇 simulation
8 篇 yield
8 篇 silicon
8 篇 critical dimensi...
7 篇 transistors
7 篇 data modeling
7 篇 design

机构

7 篇 mentor graph cor...
4 篇 cadence design s...
3 篇 univ calif berke...
3 篇 ibm corp.
3 篇 synopsys inc mou...
2 篇 kunming univ sci...
2 篇 stmicroelectroni...
2 篇 blaze dfm inc su...
2 篇 cea leti f-38054...
2 篇 cadence design s...
2 篇 cypress semicond...
2 篇 amd sunnyvale ca...
2 篇 ibm almaden res ...
2 篇 ibm corp thomas ...
2 篇 infineon technol...
2 篇 chartered semico...
2 篇 synopsys inc hil...
1 篇 mentor graph cor...
1 篇 yantai univ dept...
1 篇 design process d...

作者

6 篇 melvin lawrence ...
5 篇 boksha v
4 篇 cote m
4 篇 liebmann l
4 篇 gupta p
4 篇 capodieci luigi
4 篇 lucas k
4 篇 word j
3 篇 chen t
3 篇 wimmer k
3 篇 rieger m
3 篇 sylvester dennis
3 篇 yuan chi-min
3 篇 sharma puneet
3 篇 miloslavsky a
3 篇 heins m
3 篇 lacour p
3 篇 rody y
3 篇 hui colin
3 篇 hurat philippe

语言

203 篇 英文
1 篇 中文

检索条件"任意字段=Conference on Design and Process Integration for Microelectronic Manufacturing III"

共 204 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Proceedings of SPIE: design and process integration for microelectronic manufacturing iii

Proceedings of SPIE: Design and Process Integration for Micr...

引用

design and process integration for microelectronic manufacturing iii

The proceedings contain 44 papers from the Proceedings of SPIE: design and process integration for microelectronic manufacturing iii. The topics discussed include: design process optimization, virtual prototyping of manufacturing, and foundary-portable DFM;integrated circuit DFM framework for deep sub-wavelength processes;process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era;design of integrated-circuit interconnects with accurate modeling of chemical-mechanical planarization;manufacturing-aware design methodology for assist feature correctness;and integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches.

关键词： Optical design

来源：评论

学校读者我要写书评

暂无评论

Using yield-focused design methodologies to speed time-to-market

Using yield-focused design methodologies to speed time-to-ma...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Levitt, M Cadence Design Syst Inc San Jose CA 95134 USA

ISBN: (纸本)0819457361

As manufacturers employ emerging advances in lithographic technologies, the need for complementary improvements in design processes becomes critical. In moving to nanometer technology nodes at 90nm and below, semiconductor companies will face increased challenges for optimizing yield beyond traditional post-processing methods. Instead, increasing responsibility for yield improvement will focus on lithography-friendly design methodologies and adoption of improved design-for-manufacturability (DFM) practices able to address manufacturing yield issues from first silicon, into production ramp-up and during volume manufacturing. Among emerging DFM practices, "yield-focused" design tools and methodologies address yield-loss mechanisms arising with nanometer technologies. By employing these emerging tools and methodologies, engineers can address manufacturing-induced yield problems early in the design process and through manufacturing.

关键词： design-for-manufacturability DFM yield enhancement design methodologies time-to-market silicon-aware design automation technology design and integration

来源：评论

学校读者我要写书评

暂无评论

MAID - manufacturing aware IC design

MAID - Manufacturing aware IC design

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Scheffer, LK Cadence Design Syst San Jose CA USA

ISBN: (纸本)0819457361

design tools should take manufacturing foibles into account - on this everyone agrees. But specifically, which DFM issues should IC design software take into account, and how should they be conveyed from the fab to the design tools? Here we examine an approach that expresses four of the most pressing DFM concerns - point defect densities, via yield, lithographic process windows, and cell yield - in a way design tools can easily understand. We show these data types can be combined, they can be read quickly, and that they allow designs to be analyzed (and potentially optimized) with speeds commensurate With other existing algorithms that run on large designs. The major concern that remains is getting useful DFM data from the manufacturing firms. Without this, for example, IC design tools cannot trade off one effect against another.

关键词： DFM yield IC design lithography lithographic yield critical area via yield

来源：评论

学校读者我要写书评

暂无评论

The use of process models to enhance device performance through semiconductor design

The use of process models to enhance device performance thro...

引用

4th conference on design and process integration for microelectronic manufacturing

作者： Melvin, Lawrence S., iii Zhang, Daniel Synopsys Inc 2025 NW Cornelius Pass Rd Hillsboro OR 97124 USA

ISBN: (纸本)0819461997

As semiconductor manufacturing nodes march towards increasingly aggressive process nodes, the features that can be manufactured on a silicon wafer are becoming more and more constrained. These constraints are arising from the need for manufacturing process margin, the result of which is improved yields and wafer throughput. For less aggressive process nodes, these constraints have been transferred between the design and manufacturing communities using tables of design rules. However, as process nodes march forward, these are rules are getting complex and unmanageable. A better methodology to communicate design rules is to build a model of the manufacturing process for use by the design team. This model can then be used to analyze a piece of layout for manufacturing robustness, and allow the design to make informed layout revisions. design rules encompass effects due to many manufacturing processes including exposure, registration. etch, reticle construction, electro migration, etc. In order to create useful design rules, all of these processes must be understood and combined into a set of process rules. In order to reduce the complexity of the design rules table, a process model may be applied in complex pattern configurations. This study will seek to understand the definition of complex configurations for photolithography design rules, and it will attempt to demonstrate the usefulness of model-based design rules.

关键词： design Rule Check process model

来源：评论

学校读者我要写书评

暂无评论

Integrating RET and mask manufacturability in memory designs for local interconnect for sub-100nm trenches

Integrating RET and mask manufacturability in memory designs...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Kachwala, N Iandolo, W Brist, T Farnbach, R Cypress Semicond Inc San Jose CA 95134 USA

ISBN: (纸本)0819457361

Model based OPC for low k1 lithography has a large impact on mask cost, and hence must be optimized with respect to mask manufacturability and mask cost without sacrificing device performance. design IP blocks not designed with the lithography process in mind (not "litho friendly") require more complex RET/OPC solutions, which can in turn result in unnecessary increases in the mask cost and turn around time. These blocks are typically replicated many times across a design and can therefore have a compounding effect. design for manufacturing (DFM) techniques verify and alleviate complex interactions between design and process. DFM can be applied at various stages in your design-to-silicon flow.(1) We will discuss how these DFM methods are applied and implemented at Cypress. We will also show how design rules are defined and present several methods for injecting OPC/RET awareness into the designs prior to mask manufacture.

关键词： design for manufacturing interconnect trenches OPC PSM RET

来源：评论

学校读者我要写书评

暂无评论

Considerations for the use of defocus models for OPC

Considerations for the use of defocus models for OPC

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Sturtevant, JL Torres, JA Word, J Granik, Y LaCour, P Mentor Graph Corp Wilsonville OR 97070 USA

ISBN: (纸本)0819457361

It has been published that there is potential benefit to utilizing an OPC model based upon defocus instead of best focus processing, to give more robust patterning. While this is true with respect to gross opens and bridging problems, the available CD budget and the anticipated manufacturing consumption of defocus budgets must be considered. The net result will almost certainly always be that for gate layer processing, defocus model based OPC is not desirable. For other layers there may be favorable yield implications to running in such a manner, but the average CD in manufacturing will deviate from the design target. This paper will explore the interplay between variable focus distributions in manufacturing and the required CD control, pointing to those conditions under which a defocus model is advisable, and where it is not. Furthermore, the optimum magnitude of defocus is a compromise and has implications for final electrical performance.

关键词： model based OPC process window ORC DFM DOF

来源：评论

学校读者我要写书评

暂无评论

Geometrical analysis of product layout as a powerful tool for DFM

Geometrical analysis of product layout as a powerful tool fo...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Roessler, T Thiele, J Infineon Technol AG D-81609 Munich Germany

ISBN: (纸本)0819457361

Recently, "design for manufacturability" (DFM) has become a veritable buzzword in the semiconductor manufacturing community. DFM activities cover a broad spectrum ranging from the improvement of the electrical and structural robustness against process variations to the reduction of layout parts critical for statistically distributed defects or sensitive to systematic process weaknesses. In our work we focus only on those aspects of DFM concerned with the structural integrity of patterns on the wafer. We show that a purely geometrical analysis of product layouts offers a powerful tool to strengthen the link between design and manufacturing. It allows, for instance, a visualisation of the extent to which intra- and inter-layer design rules determine the geometry configurations dominating the layout and the identification of patterns occurring only rarely. Furthermore, in combination with the geometry-resolved information about the accuracy of "optical proximity correction" (OPC) models and "critical dimension" (CD) control, such an analysis provides valuable input for systematic improvements on both, the product layout and manufacturing process side. In this sense it supports the progress towards making real designs still manufacturable at the limits of process tool capabilities.

关键词： design for manufacturability design rules critical dimension control geometrical analysis

来源：评论

学校读者我要写书评

暂无评论

Evaluating design for manufacturing with process capability analysis

Evaluating design for manufacturing with process capability ...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： van Wingerden, J Le Cam, L Garg, M Aksenov, Y Dirksen, P Philips Res Leuven B-3001 Heverlee Belgium

ISBN: (纸本)0819457361

The shrinking of the dimensions for each new process generation increases the challenges for lithography significantly. In order to guarantee manufacturability for future process generations, a strong interaction between lithography and design is required. A quantitative measure for the manufacturability is of key importance for driving the improvements in the design for manufacturing process. Aerial image slopes or contrasts in simulated images provide a measure for the sensitivity to process variations, but do not take the statistical process variation into account. This may result in sub-optimal choices in the design for manufacturing process. This paper discusses the process capability analysis and provides an optimal design with corresponding imaging conditions, taking the statistical fluctuations of exposure dose and focus into account. The mean CD value and the CD spread are calculated as a function of the amount of variation in the process variables like focus and exposure dose. Comparing these distribution parameters to the process specifications yields the so-called process capability index as a quantitative measure for the manufacturability. Another advantage is the possibility to include the effect of mask errors on the manufacturability. Until now, however, this method had only been demonstrated for line space features. In this paper we extend the process capability analysis method for calculating the manufacturability of arbitrary layouts. The analysis is demonstrated it, an evaluation of the manufacturability of various gate layer designs, both conventional as well as litho-driven re-designs.

关键词： optical lithography process optimisation process latitudes design for manufact tiring litho driven design process capability C-pk

来源：评论

学校读者我要写书评

暂无评论

Lithography yield checking for IC design

Lithography yield checking for IC design

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Cai, L Chen, T Cadence Design Systems United States ASML MaskTools United States

ISBN: (纸本)0819457361

As the semiconductor industry goes into the 65nm generation, designs become more complex, mask cost increases exponentially, and the industry is pushing very hard on the lithography process. It is more and more challenging to achieve and maintain acceptable yield. Yield is not only a problem for the Fabs but also an issue that has to be considered by the chip designers. In order to save turn around time, save mask and process development cost and improve the yield, the lithography problems need to be resolved at the design stage. The designers need to be aware of the lithography behavior of their design and be able to modify the design if it causes yield problems in the lithography process. In this paper, we discuss a new tool, a Litho Yield Checker, which can be run stand-alone but is also fully integrated with a Layout Editor, that provides its user with an easy way to visualize how the layouts are to be printed on wafer, and see the common process window (CPW) for the most important locations in the design.

关键词： layout yield analysis lithography yield check process window analysis layout optimization OPC optimization

来源：评论

学校读者我要写书评

暂无评论

Integrating DfM components into a cohesive design-to-silicon solution

Integrating DfM components into a cohesive design-to-silicon...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Liebmann, L Maynard, D McCullen, K Seong, N Buturla, E Lavin, M Hibbeler, J IBM Systems and Technology Group (United States) IBM Corp. (United States)

ISBN: (纸本)0819457361

Two primary tracks of DfM, one originating from physical design characterization, the other from low-k(1) lithography, are described. Examples of specific DfM efforts are given and potentially conflicting layout optimization goals are pointed out. The need for an integrated DfM solution than ties together currently parallel DfM efforts of increasing sophistication and layout impact is identified and a novel DfM-enabling design flow is introduced.

关键词： design for manufacturability (DfM resolution enhancement techniques (RET physical design characterization (PDC critical area analysis (CAA restricted design rules (RDR glyph-based layout

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共21页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：