检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

201 篇 会议
3 篇 期刊文献

馆藏范围

204 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

178 篇 工学
- 119 篇 电气工程
- 118 篇 机械工程
- 31 篇 材料科学与工程（可...
- 27 篇 计算机科学与技术...
- 14 篇 电子科学与技术（可...
- 11 篇 控制科学与工程
- 11 篇 软件工程
- 5 篇 化学工程与技术
- 4 篇 仪器科学与技术
- 3 篇 光学工程
- 2 篇 冶金工程
- 2 篇 信息与通信工程
- 2 篇 测绘科学与技术
- 2 篇 纺织科学与工程
- 2 篇 环境科学与工程（可...
- 1 篇 力学（可授工学、理...
- 1 篇 轻工技术与工程
- 1 篇 船舶与海洋工程
59 篇 理学
- 50 篇 物理学
- 10 篇 数学
- 3 篇 化学
- 2 篇 系统科学
- 1 篇 海洋科学
19 篇 管理学
- 19 篇 管理科学与工程(可...
- 7 篇 工商管理
- 1 篇 图书情报与档案管...
3 篇 经济学
- 3 篇 应用经济学
2 篇 医学
- 2 篇 临床医学
1 篇 法学
- 1 篇 社会学

主题

29 篇 opc
28 篇 dfm
27 篇 lithography
21 篇 optical proximit...
19 篇 design for manuf...
18 篇 manufacturing
12 篇 photomasks
11 篇 process window
10 篇 resolution enhan...
10 篇 ret
9 篇 design for manuf...
9 篇 semiconducting w...
9 篇 optical lithogra...
8 篇 simulation
8 篇 yield
8 篇 silicon
8 篇 critical dimensi...
7 篇 transistors
7 篇 data modeling
7 篇 design

机构

7 篇 mentor graph cor...
4 篇 cadence design s...
3 篇 univ calif berke...
3 篇 ibm corp.
3 篇 synopsys inc mou...
2 篇 kunming univ sci...
2 篇 stmicroelectroni...
2 篇 blaze dfm inc su...
2 篇 cea leti f-38054...
2 篇 cadence design s...
2 篇 cypress semicond...
2 篇 amd sunnyvale ca...
2 篇 ibm almaden res ...
2 篇 ibm corp thomas ...
2 篇 infineon technol...
2 篇 chartered semico...
2 篇 synopsys inc hil...
1 篇 mentor graph cor...
1 篇 yantai univ dept...
1 篇 design process d...

作者

6 篇 melvin lawrence ...
5 篇 boksha v
4 篇 cote m
4 篇 liebmann l
4 篇 gupta p
4 篇 capodieci luigi
4 篇 lucas k
4 篇 word j
3 篇 chen t
3 篇 wimmer k
3 篇 rieger m
3 篇 sylvester dennis
3 篇 yuan chi-min
3 篇 sharma puneet
3 篇 miloslavsky a
3 篇 heins m
3 篇 lacour p
3 篇 rody y
3 篇 hui colin
3 篇 hurat philippe

语言

203 篇 英文
1 篇 中文

检索条件"任意字段=Conference on Design and Process Integration for Microelectronic Manufacturing III"

共 204 条记录，以下是11-20 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

design and process limited yield at the 65nm node and beyond

Design and process limited yield at the 65nm node and beyond

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Monahan, K Trafas, B KLA Tencor Corp Milpitas CA 95035 USA

ISBN: (纸本)0819457361

Immersion lithography at 193nm has emerged as the leading contender for critical patterning through the 32nm technology node. Super-high NA, along with attendant polarization effects, will require re-optimization of virtually every resolution enhancement technology and the implementation of advanced process control at intra-wafer and intra-field levels. Furthermore, interactions of critical dimensions, profiles, roughness, and overlay between layers will impact design margins and become severe yield limiters. In this work, we show how design margins are reduced as a result of hidden process error and how this error can be parsed into unobservable, unsampled, unmodeled, and uncorrectable components. We apply four new process control technologies that use spectroscopic ellipsometry, grating-based overlay metrology, e-beam array imaging, and simulation to reduce hidden systematic error. Feedback of super-accurate process metrics will be critical to the application of conjoint DFM and APC strategies at the 65nm node and beyond. manufacturing economics will force a trade-off between measurement cost and yield loss that favors greater expenditure on process control.

关键词： design for manufacturability DFM advanced process control APC spectroscopic ellipsometry electron microscopy grating-based overlay immersion lithography simulation yield

来源：评论

学校读者我要写书评

暂无评论

design process optimization, virtual prototyping of manufacturing & foundry-portable DFM

Design process optimization, virtual prototyping of manufact...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Hogan, J Progler, C Chatila, A Bruggeman, B Heins, M Pack, R Boksha, V Telos Venture Partners Palo Alto CA USA

ISBN: (纸本)0819457361

We consider modem design for manufacturing (DFM) as a manifestation of IC industry re-integration and intensive cost management dynamics. In that regard DFM is somewhat different from so-called design for yield (DFY) which essentially focuses on productivity (yield) management (that is not to say that DFM and DFY do not have significant overlaps and interactions). We clearly see the shaping of a new "full-chip DFM" infrastructure on the background of the "back to basics" design-manufacturing re-integration dynamics. In the presented work we are focusing on required DFM-efficiencies in a "foundry-fabless" link. Concepts of "virtual prototyping of manufacturing", "design process optimization", and "foundry-portable DFM" models are explored. Both senior management of the industry and leading design groups finally realize the need for a radical change of design styles. Some of the DFM super-goals are to isolate designers from process details and to make designs foundry portable. It requires qualification of designs at different foundries. In their turn, foundries specified and are implementing a set of DFM rules: "action-required", "recommended", and "guidelines" while asking designers to provide netlist and testing information. Also, we observe strong signs of innovation coming back to the mask industry. Powerful solutions are emerging and shaping up toward mask-centered IP as a business. While it seems that pure-play foundries have found their place for now in the "IDM+" model (supporting manufacturing capacity of IDMs) it is not obvious how sustainable the model is. Wafer as a production unit is not sufficient anymore foundries are being asked by large customers to price products in terms of good die. It brings back the notion of the old ASIC business model where the foundry is responsible for dealing with both random and systematic yield issues for a given design. One scenario of future development would be that some of the leading foundries might eventually transfo

关键词： Integrated circuit manufacture

来源：评论

学校读者我要写书评

暂无评论

A novel design-process optimization technique based on self-consistent electrical performance evaluation

A novel design-process optimization technique based on self-...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Axelrad, V Shibkov, A Lin, HJ White, D Boksha, V Thilmany, R Sequoia Design Syst Woodside CA 94062 USA

ISBN: (纸本)0819457361

Accurate manufacturing of devices at sub-wavelength nodes is becoming increasingly difficult. Lithography and lithographic process effects are quickly becoming a major concern for physical designers working at sub-wavelength process nodes. Beyond the rapidly expanding design rule deck, physical designers must have deeper access to and understanding of the process in order to grasp the full impact of layout changes on electrical performance. process aberrations, such as misalignment, are manifested as CD variation resulting in parametric shifts and systematic yield problems. These yield issues must be addressed by designers, but designers do not have adequate tools nor information to fully comprehend these issues. To correct this situation, a new approach is needed to bring information from the manufacturing process upstream into the design creation process. This work extends and generalizes concepts presented in [1-3] and presents an integrated implementation of the methodology in a complete, self-consistent flow. This methodology integrates calibrated process simulation, electrical circuit performance analysis and optionally, automatic Optical Proximity Correction (OPC) into a comprehensive design-for-manufacturing (DFM) flow. process window simulations uncover design-process interactions across multiple process variables (misalignment, bias, etc.). To characterize the process, a design of experiments qualifies the impact of design variation on electrical performance. Data. from these experiments is used to refine and calibrate process simulation models, ensuring accurate simulation. As a result, this procedure identifies critical performance and systematic yield issues prior to tapeout, eliminating costly design respins and preserving design intent.

关键词： Device simulation Transistors design for manufacturing Light sources manufacturing Lithography Field effect transistors Optical proximity correction process modeling Critical dimension metrology

来源：评论

学校读者我要写书评

暂无评论

Building an infrastructure for parametric yield analysis: Concept and implementation of a DFM platform

Building an infrastructure for parametric yield analysis: Co...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Gookassian, J Pack, B Heins, M Garcia, J Divecha, H Gordon, B Frazier, D White, D Lachinyan, G Dillon, B Suzor, C Adamov, A Min, KY Bakarian, S Marutyan, R Boksha, V HPL Technol Inc San Jose CA 95110 USA

ISBN: (纸本)0819457361

There is a growing realization of the need for highly integrated solutions enabled by new bi-directional data 'pipes' between design and manufacturing. Traditional EDA applications should be able to communicate and collaborate with yield analysis software. Simply adding such capabilities to existing EDA applications is not feasible. Thus, there is a need for an infrastructure that would enable such interaction in a standard way. We call this infrastructure the DFM Platform. In this article we present new approach to building such a platform. Brief descriptions of potential applications follow the platform architecture. "Via analysis" application includes test chips capabilities, critical area and critical parameter analysis to predict yield for a real design. The "DFM Cell Grading" module applies the concept of DFM to IP Libraries.

关键词： design for manufacturing manufacturing Photomasks Human-machine interfaces Databases Distortion Electronic design automation Semiconducting wafers Data conversion design for manufacturability

来源：评论

学校读者我要写书评

暂无评论

Toward through-process layout quality metrics

Toward through-process layout quality metrics

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Heng, FL Lee, JF Gupta, P IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)0819457361

Quality of a layout has the most direct impact in the manufacturability of a design. Traditionally, layout quality is ensured in the first order by design rules, i.e. if a layout is free of design rules violation, it is a good layout. It is assumed such a layout will be fabricated to specification. Moreover, a design rule clean layout also ensures the electrical performance of the circuit it represents. There are other layout quality measures, e.g. random defects yield of a layout is modeled by critical area, systematic defects yield is sometime measured by a weighted score of recommended design rules. All the traditional layout quality measures are computed with drawn layout shapes. In the advent of low K, lithography and the increasing variability of process technologies beyond 90nm, nominal layout quality measures need to be revisited. Traditionally, nominal electrical properties such as L-eff and W-eff are extracted from drawn layout, and the corner cases are estimated with worst case process conditions. Most of these parameters are layout pattern dependent. As a matter of fact, they can be systematic through process and can have large impact in the modeling of circuit parameters [I]. In this paper, we investigate a through process layout quality measure, in which we extract through process electrical parameters from simulated through process resist contours. We showed a mechanism to compute a statistical model that predicts through process electrical parameters from the process parameter variation. We demonstrated that such computation is practical.

关键词： Semiconducting wafers Resistance Cadmium sulfide Photomasks manufacturing Quality measurement Shape analysis Statistical analysis Optical proximity correction Photoresist processing

来源：评论

学校读者我要写书评

暂无评论

Investigating a lithography strategy for diagonal routing architecture at sub-100nm technology nodes

Investigating a lithography strategy for diagonal routing ar...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Song, L Chen, T Shah, S Joshi, K Thumaty, K Arora, N Cadence Design Syst Inc San Jose CA 95134 USA

ISBN: (纸本)0819457361

The X Architecture offers the potential to produce smaller and faster integrated circuits through the pervasive use of 45 degrees wirings on the upper metal layers. The X Initiative members have demonstrated its manufacturability and integration-worthiness at the 130nm, 90mn and 65nm process technology nodes. This paper explores the use of off-axis lithography illumination to print 45 degrees diagonal wires at leading technology nodes. The paper also describes the RET strategies employed for the X Architecture and the effectiveness of various illumination sources at various process nodes. process window and metal wiring CD variation of Manhattan and X Architecture are compared in the simulations using different types of illuminators. Simulation shows that using 193mn light source, Manhattan and X designs can easily be printed with different types of illuminating source in either 90nm or 65nm process node. Silicon test chips at 90nm that include typical X routing patterns are designed to verify the printability of X Architecture wirings. Electrical measurements as well as SEM analysis are conducted and results show that the Fidelity of diagonal wirings is as good as traditional Manhattan routings.

关键词： X Architecture diagonal wiring RET off-axis illumination process window CD uniformity

来源：评论

学校读者我要写书评

暂无评论

process centering OPC using design intent to improve yield

Process centering OPC using design intent to improve yield

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Cote, M Miloslavsky, A Lugg, R Rieger, M Hurat, P Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)0819457361

As the industry moves to 90nm and below, the size of our process windows are rapidly decreasing. The process window is often not considered during optical proximity correction (OPC) which must match the printed wafer to the original design target for a single process point. This process point is usually at 'best exposure' and 'best defocus'. The results can be verified under different defocus conditions but it is generally assumed that the printed pattern will yield well for a range of defocus and exposure conditions. At 90nm or smaller this assumption is breaking down as the final yield of products is greatly reduced due to low pattern quality under even relatively small process variations. Instead of optimizing the OPC results using a single model a multi-model approach is proposed where the pattern is optimized using two or more process points. The final printed image is optimized to both minimize the overall CD variations across a process as well as centering this variation with respect to the original target edges in CD critical areas. To maximize the benefits of this technique we also provide more freedom to OPC by making use of design intent to vary the print requirement in different areas of the design. In this paper we describe the process centering methodology and its use of design intent. To evaluate the benefits of this technique a metric is also proposed and used to quantify experimental results. Results are compared with those of a traditional OPC flow.

关键词： DFM OPC yield design intent Mask

来源：评论

学校读者我要写书评

暂无评论

Device and lithography contextual mask rule generation

Device and lithography contextual mask rule generation

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Ham, YM Dillon, B Progler, C Goldammer, K Jin, ZZ Green, G Mackay, RS Divecha, H Boksha, V Martin, P Heins, M Zhang, Y Davis, K Marutyan, R Martirosyan, K Bakarian, S Photron Austin TX 78728 USA

ISBN: (纸本)0819457361

Mask manufacturing rules are usually determined from assumed or experimentally acquired mask-manufacturing limits. These rules are then applied during resolution enhancement data treatment to guide and/or limit pattern correction strategies. This technique can be highly reactive and may not allow a careful tradeoff between the mask making capability and the end user needs. We have explored techniques to develop mask manufacturability rules in the context of wafer lithography and device needs. In this paper, we consider methods to improve the capture and usage of mask making information for resolution enhancement by applying a novel test mask and design, which is tied to a process modeling software. Mask manufacturing models are established from the test mask design and these models are applied to generate geometrical rules and continuous models linking the mask making capability to the lithography requirements. The analysis of mask manufacturing constraints is extended into the device domain through yield prediction tools that capture the impact of lithography variability on device performance. We find techniques allowing a more dynamic generation of relevant mask making constraints that can optimize both yield and cycle time in the resolution enhancement process flow. Toward this, usage cases are highlighted to illustrate the interaction of specific design layouts and our mask manufacturability.

关键词： mask rule OPC analysis RET manufacturability DFM specification design rule

来源：评论

学校读者我要写书评

暂无评论

Integrated circuit DFM framework for deep sub-wavelength processes.

Integrated circuit DFM framework for deep sub-wavelength pro...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Torres, JA Berglund, CN Mentor Graph Corp Wilsonville OR 97070 USA

ISBN: (纸本)0819457361

Until recently little has been done to formalize the concept of design for manufacturability (DFM) for integrated I circuits. This is a complex problem that has been addressed from multiple angles with different degrees of success. While there can be certain operations which improve one manufacturability component, they can also adversely affect another. For this reason a framework that systematically addresses multiple manufacturability tradeoffs is required. This work proposes a pattem-centric DFM framework which emphasizes pattern robustness and introduces the concept of process variability bands (pv-Bands) to create a ranking system to measure the manufacturability of any design. The ranking system is composed of manufacturability indices, and their behavior is presented for different process nodes as well as across multiple processing layers (i.e. metal1, active, poly, etc). As an example of the necessity of such a framework, lithography-compliant rules are defined to suggest how other manufacturing processing steps need to be characterized in order to be successfully integrated in the framework. Examples of pinching (necking), bridging and CD control rules based on a pv-Band description are also discussed. In addition this work includes a description on how the process models derived from this study can be used to improve electrical analysis via a more accurate device description. As an example, timing-process-windows are defined as the link between design requirements and pattern manufacturability, and indicate why electrical models need to explicitly account for pattern induced effects at conditions other than nominal.

关键词： DFM microlithography litho-compliant RET-compliant timing analysis process models OPC

来源：评论

学校读者我要写书评

暂无评论

Assessing the impact of real world manufacturing lithography variations on post-OPC CD control

Assessing the impact of real world manufacturing lithography...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Sturtevant, JL Word, J LaCour, P Park, JW Smith, D Mentor Graph Corp Wilsonville OR 97070 USA

ISBN: (纸本)0819457361

This paper investigates variability across multiple lithographic domains, as experienced in typical manufacturing environments, and assesses the impact on achievable post-OPC image Fidelity and CD control. Across scanner field and tool-tool effects are considered, and a distinction is made between systematic phenomena, which typically manifest within chip, and random fluctuations, which predominantly impact chip-to-chip mean distributions. The paper will outline which lithographic parameters can effectively be accounted for in OPC models, and over what temporal/spatial extents. The non-correctable phenomena assessed include misalignment, projection optic aberrations, illumination source profile, mask CD, focus and exposure dose variation, and flare. Specific analyses are applied to the case of gate edge placement error (EPE) control as a function of these manufacturing variables. Recommendations are made for "field-aware" metrology sample plans during model creation such that globally optimized models can be realized. With knowledge of manufacturing input parameter variation, Caiibre (TM) enables a detailed understanding or realistic post-OPC CD control, and can guide judicious product metrology sampling and specifications. It is highlighted that even for the case of a "perfect" OPC model, the post-OPC CD variation within chip can still be substantial, due to manufacturing variability.

关键词： model based OPC process window ORC DFM DOF misalignment aberrations flare

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共21页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：