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检索条件"任意字段=Conference on Design and Process Integration for Microelectronic Manufacturing III"

共 204 条记录，以下是21-30 订阅

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process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era

Process-window sensitive full-chip inspection for design-to-...

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conference on design and process integration for microelectronic manufacturing iii

作者： Brodsky, MJ Halle, S Jophlin-Gut, V Liebmann, L Samuels, D IBM Corp Microelect Div Hopewell Jct NY USA

ISBN: (纸本)0819457361

As lithographers continue to implement more exotic and complex Resolution Enhancement Techniques (RET) to push patterning further beyond the physical limits of optical lithography, full-chip brightfield inspections are becoming increasingly valuable to help identify, random and systematic defects that occur due to mask tolerance excursions, OPC inaccuracies, RET design errors, or unmanufacturable layout configurations. PWQ, or process Window Qualification, is a KLA-Tencor product* using brightfield imaging inspection technology that has been developed to address the need for rapid full-chip process window verification. PWQ is currently implemented at IBM's 300mm facility and is being used to isolate features that repeatedly fail as a function of exposure dose and focus errors. We will demonstrate how PWQ results have assisted in: 1) qualification of reticles and new OPC models;2) identification of non-obvious lithographic features that limit common process windows;3) providing input for long-term design for manufacturability (DJM), OPC, and/or RET modeling. PWQ allows full or partial chips to be scanned in far less time than a multi-point common process window collected on a SEM. PWQ findings supplement these traditional analysis methods by encompassing all features on a chip, providing more detail on where the process window truly lies. Examples of marginal features that were detected by PWQ methods and their subsequent actions will be discussed in this paper for an advanced 65nm and a 90nm CMOS process.

关键词： process window verification and qualification design for manufacturing brightfield imaging wafer inspection techniques

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Inspection of integrated circuit databases through reticle and wafer simulation: An integrated approach to design for manufacturing (DFM)

Inspection of integrated circuit databases through reticle a...

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conference on design and process integration for microelectronic manufacturing iii

作者： Howard, W Azpiroz, JT Xiong, YL Mack, C Verma, G Volk, W Lehon, H Deng, YF Shi, RF Culp, J Mansfield, S KLA Tencor Austin TX 78759 USA

ISBN: (纸本)0819457361

The present approach to Optical Proximity Correction (OPC) verification has evolved from a number of separate inspection strategies. OPC decoration is verified by a design rule or optical rule checker, the reticle is verified by a reticle inspection system, and the final wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with little or no data flowing between them. In this paper, we will report on a new inspection system called designScan that connects the data between the various abstraction layers. designScan inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure process window. The simulated images are compared to the desired pattern and defect detection algorithms are applied to determine if any unacceptable variations in the pattern occurs within the nominal process window. The end result is a new paradigm in design verification, moving beyond OPC verification at the design plane to process window verification at the wafer plane where it really matters. We will demonstrate the application of designScan to inspect full chip designs that utilized different Resolution Enhancement Technique (RET) and OPC methods. In doing so, we'll demonstrate that designScan can identify the relative strengths and weaknesses of each methodology by highlighting areas of weak process window for each approach. We will present experimental wafer level results to verify the accuracy of the defect predictions.

关键词： designScan DFM process window PROLITH simulation

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Lithography simulation system for total CD control from design to manufacturing

Lithography simulation system for total CD control from desi...

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conference on design and process integration for microelectronic manufacturing iii

作者： Kotani, T Ichikawa, H Kobayashi, S Nojima, S Izuha, K Tanaka, SS Inoue, S Toshiba Corp. (Japan) Toshiba Microelectronics Co. (Japan)

ISBN: (纸本)0819457361

Systematic design for manufacturability (DfM) scheme including triple gates for hot spot elimination under the low-k(1) lithography condition is proposed and efficient approaches to the hot spot elimination at each development stage in the DfM scheme are discussed in view of the actual situation under the concurrent development of design rule (DR), layout, process, optical proximity correction (OPC) and resolution enhancement technique (RET) technologies. Integrated-type lithography simulation system with OPC tool is much available for the fast processing at the initial stage and promising to be complementarily used for the verification of chip-level layout with conventional-type one at the final development stage. Low order of the lithography empirical model originating moderate prediction accuracy for all kinds of patterns is hopeful to be used at the initial development stage because it is difficult to obtain a lot of reliable experimental data for making the accurate empirical lithography model due to frequent improvement of the process, OPC and RET technologies. At the final development stage, sufficient and reliable experimental data for device pattern variations allow us to implement the higher order of the empirical model. The DIM scheme with efficient approaches in view of the actual situation under the concurrent development is found to be promising for the robust pattern formation under the low-k(1) lithography condition.

关键词： design rule DfM OPC RET manufacturability check lithography simulation system hot spot empirical lithography model concurrent development

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Library-based process test vehicle design framework

Library-based process test vehicle design framework

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conference on design and process integration for microelectronic manufacturing

作者： Doong, KYY Hung, LJ Ho, S Young, KL Lin, SC Taiwan Semicond Mfg Corp Shinchu 300 Taiwan

ISBN: (纸本)0819448478

This work describes a test vehicle design framework, which minimizes the discrepancy among design rule set, test structure design and testing plan. The framework is composed of the symbolic design rule set, Parameterized-Device, test structure generator, and test vehicle generator. An approach for simplification and consolidation of test structure is proposed to derive the concise test structure library. Finally, implementation of test vehicle is presented.

关键词： test structure test vehicle logic process SoC electronic design automation synthesis migration

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Mask cost reduction and yield optimization using design intent

Mask cost reduction and yield optimization using design inte...

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conference on design and process integration for microelectronic manufacturing iii

作者： Cote, M Miloslavsky, A Hurat, P Rieger, M Goinard, D Synopsys Inc Mountain View CA 94043 USA

ISBN: (纸本)0819457361

The relentless pursuit of Moore's Law is pushing lithographical equipment to its limits. Extensive use of Resolution Enhancement Technologies (RET) during mask synthesis has allowed the industry to meet demand for density and performance at the 0.13um node and below. RET has been used to sustain the traditional model of printing edges as close as possible to the corresponding edges in the design layout. As technology moves to sub-100nm processes this model is proving to be both challenging and expensive to sustain. Pushing the RET tools to do an aggressive match between layout geometries and the printed pattern results in a large increase in mask cost. Even if this optimization is successful the resulting pattern may not provide the highest possible yield. In previous papers(1) we demonstrated the use of design intent(2) (DI) during mask synthesis to both reduce mask cost and improve yield. In this paper more results are described of how much improvement is possible on mask shot count and sliver count. We also investigate the cell level timing impact of our proposed methodology. Detailed timing results are presented and analyzed along with their impact on the design flow.

关键词： DFM OPC yield design intent mask timing cost

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Lithography window check before mask tape-out in sub 0.18um technology

Lithography window check before mask tape-out in sub 0.18um ...

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4th conference on design and process integration for microelectronic manufacturing

作者： Lu, Mark King, Dion Li, Flora Mao, Zhibiao Liang, Curtis Melvin, Lawrence S., iii Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol Shanghai 200050 Peoples R China

ISBN: (纸本)0819461997

Lithography Rule Check (LRC) becomes a necessary procedure for post OPC in 0.15um LV and below technology in order to guarantee mask layout correctness. LRC uses a process model to simulate the mask pattern and compare its performance to the desired layout. When the results are out of specified tolerances, LRC will generate error flags as weak points to trigger further checks. This paper introduces LRC to detect the weak points even in non-OPC employed circuit layout such as 0.18um to 0.15um process. LRC is more important for semiconductor foundry since there are diverse design layouts and shrinks in production. This diversity leads to the possibility of problematic structures reaching the reticle. In this work, LRC is added as a necessary step in tape-out procedure for the sub 0.18um process nodes. LRC detected weak points such as low or excessive contrast sites, high MEEF areas and small process window features, then modified the layout according to check results. Our work showed some mask related potential problems can be avoided by LRC in even non model based OPC process and therefore guarantee improved product yield.

关键词： Lithography Rule Check LRC weak points layout OPC

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Detecting focus-sensitive configurations during OPC

Detecting focus-sensitive configurations during OPC

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conference on design and process integration for microelectronic manufacturing iii

作者： Melvin, LS Shiely, JP Yan, QL Synopsys Inc Hillsboro OR 97124 USA

ISBN: (纸本)0819457361

Model-based optical proximity correction (OPC) calculates pattern adjustments by simulating the layout with calibrated lithography and process models. OPC can only correct systematic lithography deviations - those error components that repeat chip to chip. OPC cannot compensate random deviation error components from unpredictable process variations, such as defocus and dose. However the ranges of variation from random effects is predictable, and OPC can optimize correction shapes to minimize this range where possible. Current techniques for supporting this optimization involve applying a set of models covering the range of expected process variations in defocus and exposure. Variation is assessed by comparing process corner-point model evaluations. Because there is a significant runtime cost simulating multiple process conditions, most production OPC jobs use a single, representative model (typically the "nominal" process condition) aided with rules and other heuristics to help handle process window effects. In this paper the application of a new type of model that can be used to predict process variation with a single simulation call. The model involved in these studies targets pattern behavior as the focus offset deviates from the nominal focus setting. Used in conjunction with a nominal process model, this model can support process-window optimized OPC without the need for multiple models at various defocus settings. This model can also be used by itself to assess the defocus robustness of any configuration before or after OPC, thereby supporting efficient model-based layout verification.

关键词： process window process window optimization process variation OPC

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design rule considerations for 65 nm node contact using off axis illumination

Design rule considerations for 65 nm node contact using off ...

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conference on design and process integration for microelectronic manufacturing iii

作者： Jessen, S Mason, M O'Brien, S Terry, M Soper, R Wolf, T Texas Instruments Inc Dallas TX 75243 USA

ISBN: (纸本)0819457361

Perhaps the most critical lithographic challenge at the 65 nm node can be found printing contact holes for random logic. Achieving all pitches from dense to isolated simultaneously in a single mask print requires high numerical aperture (NA) with novel low-k1 imaging techniques. As is typical in complex engineering problems, requirements compete against each other. The requirement to achieve the desired dense resolution suggests the use of off axis illumination (OAI) techniques such as annular and Quasar (TM). At the same time, the need to meet other figures of merit (FOM) such as depth of focus (DOF) and mask error enhancement factor (MEEF) for larger pitches are strong considerations for choosing the more conventional illumination conditions. Morever, previously unconsidered FOMs such as contact asymmetry and displacement must now also be strongly considered. In particular, we discuss design limitations which may be incorporated to avoid fundamental patterning issues when using OAI and sub-resolution assist features (SRAF) for printing CT level at 65 nm node.

关键词： Contact Hole low-kl imaging ArF

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DFM through correct process construction

DFM through correct process construction

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conference on design and process integration for microelectronic manufacturing II

作者： Qian, QD IC Scope Res Inc Santa Clara CA 95051 USA

ISBN: (纸本)0819452920

Layout engineering is the link in the design flow with the highest degree of freedom for manufacturability optimization. Generating correct lithography-ready mask data as part of layout design would significantly shorten product's time to market. Until recently, however, a layout designer has no way of evaluating the manufacturability beyond design rules. In this paper, we propose to integrate a comprehensive manufacturability preview capability into the layout design environment. Based on the feedback from process simulation, a correct by construction approach for generating manufacturing friendly layout is proposed. It consists of selective mask optimization and process weak spot detection. We demonstrate the advantage of correct process construction using MOSIS standard cell library and discuss its future applications.

关键词： DFM pattern transfer photolithography mask simulation OPC

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design-to-process integration: optimizing 130 nanometer X Architecture manufacturing

Design-to-process integration: optimizing 130 nanometer X Ar...

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conference on design and process integration for microelectronic manufacturing

作者： Dean, B Malhota, V King, N Sanie, M MacDonald, S Jordan, J Hirukawa, S

ISBN: (纸本)0819448478

The X Architecture is a novel on-chip interconnect architecture based on the pervasive use of diagonal wiring. This diagonal wiring reduces total chip wire length by an average 20% and via count by an average of 30%, resulting in simultaneous improvements in chip speed, power, and cost. Thirty percent or greater reduction in via counts is a compelling feature for IC design - but can chips with massive amounts of diagonal wiring be manufactured without some other penalty? This paper presents the results of a project, collaborated by Cadence design Systems, Numerical Technologies, DuPont Photomasks, and Nikon, aimed at optimizing each step of the lithography supply chain for the X Architecture from masks to wafers at 130 nm.

关键词： X Architecture lithography photomask wafers manufacturability OPC via wire reticle

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