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检索条件"任意字段=Conference on Design and Process Integration for Microelectronic Manufacturing III"

共 204 条记录，以下是31-40 订阅

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Full chip gate CD error prediction for model-based OPC

Full chip gate CD error prediction for model-based OPC

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Shu, VY Choi, B Quek, SF Adv Module Tech Dev Chartered Semicond Singapore 738406 Singapore

ISBN: (纸本)0819457361

In this paper, a technique for full chip gate CD(critical dimension) error prediction based on empirical models will be presented and discussed. In order to be compatible with existing common terminologies, this technique can also be called model-based full chip gate CD verification, which has become an integral part of closed-loop design-to-silicon flow of gate layer masking processes at 90nm and 65nm technology nodes. The empirical optical-and-process models can be same or different (such as with defocus) from the ones which are widely used in model based OPC and ORC. Similar to but different from conventional ORC, which normally addresses the minimum feature check or fatal error check, the model-based gate CD verification technique will focus on CD error prediction and CD error distribution analysis for gate CD related yield improvement efforts. Current commercial ORC or model-based verification tools provide the capability of EPE (edge placement error) check and analysis, and with certain additional techniques they may also provide the capability of gate CD prediction or simulation for selected targets or figures. The new model-based gate CD verification technique will provide the capability of full chip CD error prediction and CD error distribution analysis for all concerned small gate CD targets.

关键词： full chip verification design-to-silicon flow model-based OPC ORC lithography CD variation

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Minimizing mask complexity for advanced optical lithography

Minimizing mask complexity for advanced optical lithography

引用

conference on design and process integration for microelectronic manufacturing II

作者： Fritze, M Tyrrell, B MIT Lincoln Lab Lexington MA 02420 USA

ISBN: (纸本)0819452920

The extension of optical lithography to ever deeper sub-wavelength feature sizes has led to an alarming increase in photo-mask complexity and associated cost. Changes in design philosophy can play a key role in mitigating this trend. We propose the introduction of a new optimization cycle early in the physical design process based on minimizing pattern complexity. We study the use of a pattern complexity metric based on Fourier coding to accomplish such an optimization. The ultimate goal is simplification of resolution enhancement technology (RET) methods required for a given design and the generation of a correspondingly simpler and more cost effective mask set.

关键词： mask complexity mask cost design for manufacturing RET optimization

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Sequential PPC and process-window-aware mask layout synthesis

Sequential PPC and process-window-aware mask layout synthesi...

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4th conference on design and process integration for microelectronic manufacturing

作者： Sezginer, Apo Zach, Franz X. Yenikaya, Bayram Carrero, Jesus Huang, Hsu-Ting Invarium Inc San Jose CA 95110 USA

ISBN: (纸本)0819461997

We present a full-chip implementation of model-based process and proximity compensation. Etch corrections are applied according to a two-dimensional model. Lithography is compensated by optimizing a cost function that expresses the design intent. The cost function penalizes edge placement errors at best dose and defocus as well as displacement of the edges in response to a specified change in a process parameter. This increases immunity to bridging in low contrast areas.

关键词： Etching Photomasks process modeling Lithography Model-based design Data modeling Photoresist processing Tolerancing Image processing Semiconducting wafers

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Trends in systematic non-particle yield loss mechanisms and the implication for IC design

Trends in systematic non-particle yield loss mechanisms and ...

引用

conference on design and process integration for microelectronic manufacturing

作者： Berglund, CN NW Technol Grp Vancouver WA 98684 USA

ISBN: (纸本)0819448478

Semiconductor industry yield trends from the 500 nm generation through the 180 nm generation are described that illustrate traditional random defect yield loss mechanisms have been found to be less and less important relative to the yield loss caused by systematic and primarily non-particle mechanisms as semiconductor processes have moved to sub-wavelength lithography. While part of the reason for this is the continued particulate defect reduction success due to better equipment and fab procedures, a more important reason is the increase in systematic mechanisms driven in large part by the rapidly increasing process complexity and decreasing process parameter "windows" required as processes moved through the generations. In this paper these yield loss trends are reviewed and projected to the 130nm and beyond technology nodes, and the implications for effective IC design and design methodology discussed.

关键词： yield defects systematic mechanism limited yield design for manufacturing

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DFM in practice - Results of a three way partnership between a leading fabless design house, foundry, and EDA company to implement alternating-phase shift mask (Alt-PSM) on a 90nm FPGA chip

DFM in practice - Results of a three way partnership between...

引用

conference on design and process integration for microelectronic manufacturing iii

作者： Yu, CC Shieh, MF Liu, E Lin, B Lin, H Chacko, M Li, X Lei, WK Ho, J Wu, X UMC Tainan 741 Taiwan

ISBN: (纸本)0819457361

At the sub 90nm nodes, resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential steps in the post-physical verification 'Mask Synthesis' process and a key component of design for manufacturing (DFM). Several studies have been conducted and the results have been published on the implication and application of the different types of RETs on mask printability and costs. More specifically, double-exposure-based, dark-field, alternating PSM (Alt-PSM) technology has received lot of attention with respect to the mask manufacturing challenges and its implementation into a production flow, despite its yield and critical dimension (CD) control superiority. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a matured, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. What follows is an in-depth review of the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

关键词： phase-shifting mask (Alt-PSM) phase conflict DFM. 90nm node CD control

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OPC methods to improve image slope and process window

OPC methods to improve image slope and process window

引用

conference on design and process integration for microelectronic manufacturing

作者： Cobb, N Granik, Y Mentor Graph Corp San Jose CA 95131 USA

ISBN: (纸本)0819448478

In this paper, we use the gradient of the image slope and gradient of the edge placement error (EPE) in order to improve both slope and EPE during OPC. The EPE gradient taken with respect to edge position is normally called MEEF or more generally, the MEEF matrix. Use of the gradient of image slope with respect to change in edge position is a relatively new concept, introduced by Granik as the "contrast matrix" [1,2,3]. Whereas traditional OPC techniques focus on EPE alone (pattern fidelity), we broaden the scope of OPC to maximize slope for improved image robustness and to maximize process window.

关键词： MEEF OPC process window

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The use of optical proximity correction to compensate for reflectivity differences in n type and p type poly-silicon

The use of optical proximity correction to compensate for re...

引用

4th conference on design and process integration for microelectronic manufacturing

作者： Melvin, Lawrence S., iii Huang, Jensheng Synopsys Inc Synopsys Technol Pk2025 NW Cornelius Pass Rd Hillsboro OR 97124 USA

ISBN: (纸本)0819461997

Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to fully control those interactions, different processes typically have variations that can cause significant deviation of the properties of printed integrated circuit. However, if a process variation is predictable and systematic, OPC techniques can successfully be applied to compensate for those process variations by modifying the layout. One such process variation relates to topographic variation on a wafer surface, which can cause defocusing during an optical lithography process. The nominal-focus aerial image of the layout should ideally be coincides with the wafer surface. In reality, topographic variation on the wafer surface can cause portions of the wafer's surface to be deviated from the nominal focal plane. This can result in defocused aerial-image on the wafer causing line width variation of transistor gates during manufacturing process. This problem can be minimized by using anti-reflective coatings as well as differential biasing of the n-type, n-type, and field polysilicon. However, even after application of these two techniques, some residual error remains because the ARC layers are not fully absorbent. Moreover. the biasing techniques also induce process problems at the transition point between the biases and unbiased gate regions. In fact, required applied biases gradually become difficult to manage during technology node migrations. This paper presents a system that accurately determines critical dimension layout by compensating for the effects of topography variation on the performance of an optical lithography process. In this study, a model form and its empirical calibration process have been presented.

关键词： optical proximity correction reflectivity differences in n-type and p-type polysilicon

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New OPC methods to increase process margin for sub-70nm devices

New OPC methods to increase process margin for sub-70nm devi...

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conference on design and process integration for microelectronic manufacturing iii

作者： Hong, JS Kim, DH Kim, SW Yoo, MH Kong, JT SAMSUNG Electronics Co. Ltd. (South Korea)

ISBN: (纸本)0819457361

Current model-based OPC methods are targeting the critical dimension and the fidelity of the design layout. These methods cannot suitably consider the process margin and reveal several problems below 70nm design layout with the low k1 process factor. Although litho-friendly layout methods have been introduced to improve the photolithography process margin, designing perfect litho-friendly layout is difficult because or the designer's lacking of knowledge about the process and the relationship between the layers. Thus we have developed new OPC methods to increase the process margin for sub-70nm process. In this paper we propose new methods to generate the OPC-friendly layout from the original design by 1) rule-based retargeting, 2) model-based retargeting using NILS values, and 3) model-based retargeting by MEEF values. In addition, we have evaluated the post-processing treatment by NILS or MEEF values after the model-based OPC. The proposed OPC methods are effective for the memory bit line layer and metal layers, which are composed of the complicated 2-dimensional configuration and also have the advantage to compensate the model inaccuracy for the layout having non-periodic pattern structure. While the rule-based retargeting method requires high engineering cost to optimize the retargeting rule, the model-based retargeting method can be easily implemented into the conventional OPC process and do not need the extraction process of the retargeting rule which is not simple for the 2-dimensional patterns. Applying the model-based retargeting we could increase the DOF margin by 50% compared to the normal OPC method for sub-70nm memory device with ArF lithography. It is more effective to use these retargeting methods from the defocused OPC models.

关键词： model-based OPC process margin lithography OPC-friendly layout retargeting

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Lithographic tradeoffs between different assist feature OPC design strategies

Lithographic tradeoffs between different assist feature OPC ...

引用

conference on design and process integration for microelectronic manufacturing

作者： Word, J Zhu, SH Integrated Device Technol Hillsboro OR 97124 USA

ISBN: (纸本)0819448478

In recent years many of the problems associated with the use of assist features have been partially or completely resolved. Such issues include mask manufacturing and inspection, software maturity, and the so-called forbidden pitch problem. Still, the lithographer is faced with numerous choices in developing production worthy assist feature designs. This paper will examine some of the choices, and the tradeoffs associated with each. In particular the choice between simple one-dimensional scatter bar designs and various two-dimensional designs will be explored to determine the tradeoffs. with lithographic performance. A DRC (design Rule Check) -driven technique has been developed to highlight potential shortcomings of each individual design strategy. The lithographic impact of these shortcomings has been confirmed with on-Silicon process data.

关键词： scatter bar assist feature SRAF OPC RET DRC

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Investigation of model-based physical design restrictions

Investigation of model-based physical design restrictions

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conference on design and process integration for microelectronic manufacturing iii

作者： Lucas, K Baron, S Belledent, J Boone, R Borjon, A Couderc, C Patterson, K Riviere-Cazaux, L Rody, Y Sundermann, F Toublan, O Trouiller, Y Urbani, JC Wimmer, K Freescale Semicond F-38926 Crolles France

ISBN: (纸本)0819457361

As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions [1]. Therefore, similar to the semiconductor industry's transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques [2]. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.

关键词： Model-based design Optical proximity correction Data modeling Optical lithography Lithography Systems modeling Semiconductors Resolution enhancement technologies Reticles Semiconducting wafers

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