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检索条件"任意字段=Conference on Design and Process Integration for Microelectronic Manufacturing III"

共 204 条记录，以下是61-70 订阅

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High-performance circuit design for the RET-enabled 65nm technology node

High-performance circuit design for the RET-enabled 65nm tec...

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conference on design and process integration for microelectronic manufacturing II

作者： Liebmann, L Barish, A Baum, Z Bonges, H Bukofsky, S Fonseca, C Halle, S Northrop, G Runyon, S Sigal, L IBM Microelect Semicond Res & Dev Ctr Armonk NY 10504 USA

ISBN: (纸本)0819452920

The implementation of alternating phase shifted mask lithography for the poly-conductor level of IBMs leading edge 65mn microprocessor is described. Very broad and 'resolution-enhancement-technology generic' design rules, referred to as radical design restrictions, are demonstrated to be key enablers of alternating phase shifted mask design. The benefit of these radical design restrictions over conventional design rules and other alternating phase shifted mask design approaches is detailed for key aspects of the design flow.

关键词： layout optimization resolution enhancement techniques (RET) radical design restrictions (RDR)

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Impact of process variation on 65nm across-chip linewidth variation

Impact of process variation on 65nm across-chip linewidth va...

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4th conference on design and process integration for microelectronic manufacturing

作者： Hong, Le Brist, Travis LaCour, Pat Sturtevant, John Niehoff, Martin Niedermaier, Philipp Mentor Graph Corp Wilsonville OR 97070 USA Mentor Graph Corp Munich Germany Infineon Technol AG Munich Germany

ISBN: (纸本)0819461997

The latest improvements in process-aware lithography modeling have resulted in improved simulation accuracy through the dose and focus process window. This coupled with the advancements in high speed, full chip grid-based simulation provide a powerful combination for accurate process window simulation. At the 65nm node, gate CD control becomes ever more critical so understanding the amount of CD variation through the full process window is crucial. This paper will use the aforementioned simulation capability to assess the impact of process variation on ACLV (Across-Chip Linewidth Variation) and critical failures at the 65nm node. The impact of focus, exposure, and misalignment errors in manufacturing is explored to quantify both CD control and catastrophic printing failure. It is shown that there is good correlation between predicted and experimental results.

关键词： OPC ACLV CD variation gate verification

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Optical extensions integration for a 0.314μm² 45nm node 6-transistor SRAM cell

Optical extensions integration for a 0.314μm<SUP>2</SUP> 45...

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conference on design and process integration for microelectronic manufacturing iii

作者： Verhaegen, S Nackaerts, A Wiaux, V Hendrickx, E Vandenberghe, G IMEC VZW B-3001 Louvain Belgium

ISBN: (纸本)0819457361

A target of the 45mn node development at IMEC is to produce a working 6-transistor SRAM (6-T SRAM) cell. Here we describe the lithographic solutions for this challenge. Following the requirements of the ITRS Roadmap requires challenging k(1) values. A classical 6-transistor SRAM design is difficult to scale to lower k(1) values for imaging and overlay reasons. In this paper we discuss the litho friendly design that was used to originally produce a working 0.314 mu m(2)45nm node 6-transistor SRAM cell. The design was scaled to a k(1) value of 0.31 for printing the active area layer on a 0.75NA ArF scanner at IMEC. Later on this was further scaled to a k(1) of 0.280 and a cell size of 0.274 mu m(2) for a working cell and imaging with a k(1) of 0.265 on a higher NA tool. Various resolution enhancement techniques have been used for the three most critical layers of the SRAM eel I: active area, poly gates and contact holes. Although designed unidirectional, the active area and the poly layer of the SRAM cell have critical features in two directions and therefore choosing the right illuminator shape is not straightforward. A pupil shape optimizer was used to maximize the contrast of the aerial image of the various critical features in these layers. For the contact layer the minimal pitch in the design is 160nm, which corresponds to a k(1) of 0.31. The pattern was split up into two images to increase the minimum pitch for the imaging to 190nm. Since off-axis illumination is used to print the 190nm pitch, assist features are added to the more sparse features. Contacts are not placed on a regular rectangular grid and additionally non-square contacts are used for local interconnects. This complicates the placement of the assist features and the interference mapping lithography (IML (TM)) technology was used to help in this task. The split design has been used in a double patterning approach in the SRAM process flow. In this paper we show that all the above-mentioned resolutio

关键词： Photolithography

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Combining OPC and design for printability into 65nm logic designs

Combining OPC and design for printability into 65nm logic de...

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conference on design and process integration for microelectronic manufacturing II

作者： Lucas, K Yuan, CM Boone, R Strozewski, K Porter, J Tian, RQ Wimmer, K Cobb, J Wilkinson, B Toublan, O Motorola Inc Semicond Prod Sector F-38926 Crolles France

ISBN: (纸本)0819452920

The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.

关键词： optical proximity correction OPC lithography design for manufacturability DFM

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Taming pattern and focus variation in VLSI design

Taming pattern and focus variation in VLSI design

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conference on design and process integration for microelectronic manufacturing II

作者： Heng, FL Gupta, P Lai, KF Gordon, R Lee, JF IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)0819452920

Tight ACLV control has become increasingly difficult due to the diminishing process constant, K1. Focus variation and pitch variation are two major systematic components of ACLV. In this paper, we demonstrate these systematic effects and propose a design flow which exploits the systematic effect. We demonstrate the systematic ACLV by showing a Bossung plot for a nominal 90mn technology node. The plot is generated by simulation with lithographic parameters closely resembling a production technology node. Traditionally, tight CD control is achieved by sophisticated RET such as OPC, SRAF, AltPSM and more recently the Dense Template design.(1) The CD variation is specified in the design manual and the circuit designs will ensure functionality by building in enough margin to account for the variability. Even though, the systematic components of CD variation are understood, they have Always been considered together with other random components as being random. This approach has left design performance on the table. We propose a holistic design flow by integrating the technology development process, design process and the manufacturing process. This holistic approach is aiming to tame the systematic through-pitch and through-focus CD variation. We quantify the design timing benefit using this approach by circuit design experiments. Results of our experiments show that timing uncertainty can be reduced by up to 30%. We also discuss other possibilities which are infeasible to carry out in traditional approach with silos of technology development, design and manufacturing.

关键词： ACLV systematic variation through-focus variation through-pitch variation

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Investigation of product design weaknesses using model-based OPC sensitivity analysis

Investigation of product design weaknesses using model-based...

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conference on design and process integration for microelectronic manufacturing

作者： Postnikov, S Lucas, K Garza, C Wimmer, K LaCour, P Word, J Motorola Inc Adv Prod Res & Dev Lab Austin TX 78721 USA

ISBN: (纸本)0819448478

Due to the challenging CD control and resolution requirements of future device generations, a large number of complex lithography enhancement techniques are likely to be used for random logic devices [1]. This increased design, reticle, process and OPC complexity must be handled flawlessly by process engineers in order to create working circuits. Additionally, the rapidly increasing cost and cycletime of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have extended the capability of leading edge model-based OPC software to find and analyze process-limiting regions in real product designs [2]. Specifically, we have implemented and verified software usefulness to find design-process limitations due to measured lens aberrations, as well as errors in focus, exposure or reticle CD control. We present results showing the applications and limitations of these new model-based analysis methods to discover process-design interaction errors in 90nm and 130nm patterning processes;and to propose design rule, process or OPC improvements to mitigate these errors.

关键词： Optical proximity correction Reticles Error analysis Semiconducting wafers Model-based design Optical lithography Atrial fibrillation Data modeling Product engineering Lithography

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design-friendly DFM rule

Design-friendly DFM rule

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4th conference on design and process integration for microelectronic manufacturing

作者： Osawa, Morimi Minami, Takayoshi Futatsuya, Hiroki Asai, Satoru Fujitsu Ltd Akiruno Technol Ctr 50 Fuchigami Tokyo 1970833 Japan

ISBN: (纸本)0819461997

We proposed a design-friendly DFM rule intended to improve circuit performance. To reduce variations in the gate length, we applied active usage of preferred gate spaces and optimized the lithographic conditions. We selected the spaces to take into account the layouts that are used most frequently in actual design, so that many designers who are worrying about chip area and performance can follow the rule. The effect of our method was evaluated for 65-nm node technology. From the viewpoint of gate length, parallel usage of design following the rule and optimization lead to an 8% decrease in variation, and a 38% decrease in the mean difference from the targeted gate length. We also evaluated the effect on delays using an accurate method that can treat both statistical and systematic variation. The difference in the average delay from the tar targeted value was reduced from about 1% to less than 0.1%, and a 10% improvement in delay variation was observed.

关键词： DFM preferred rule recommended rule litho-friendly design standard cell gate length variation

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Proceedings of SPIE - design and process integration for microelectronic manufacturing II

Proceedings of SPIE - Design and Process Integration for Mic...

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PROCEEDINGS OF SPIE SPIE - The International Society for Optical Engineering: design and process integration for microelectronic manufacturing II

The proceedings contains 41 papers from the conference on the Proceedings of SPIE- design and process integration for microelectronics manufacturing II. Topics discussed include: dense-only phase-shift template lithography;assessing technology options for 65-nm logic circuits;performance-impact limited-area fill synthesis;simulation-based data processing using repeated pattern identification and lithography-driven layout of logic cells for 65-nm node.

关键词： Photolithography

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Challenges and solutions for trench lithography beyond 65nm node

Challenges and solutions for trench lithography beyond 65nm ...

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4th conference on design and process integration for microelectronic manufacturing

作者： Lu, Zhijian (George) Ho, Chi-Chien Mason, Mark Anderson, Andrew Mckee, Randy Jackson, Ricky Zhu, Cynthia Terry, Mark 13560 North Cent Expressway Dallas TX 75243 USA

ISBN: (纸本)0819461997

Due to complex interconnect wiring scheme and constraints from process rules, systematic defects such as pattern necking and bridging are a major concern for metal layers. These systematic defects or "weak spots" can be major yield detractors in IC manufacturing if not properly addressed. These defects can occur even in cases where model-based OPC has been implemented, as well as a variety of process rules for margin insurance. Determining how to improve the marginalities or "weak spots" becomes a key factor for enhancing product yields. This paper will address several root causes for pattern induced defects and present solutions to a variety of weak spots including "T-shape," "H-shape," "Thin-Line," and "Bowling Pin" defects during 65nm product development at TI. Through case studies, we demonstrate how to successfully provide DFM (design for manufacturing) by using Resolution Enhancement Techniques (RET) tools to avoid and minimize the weak spots. Furthermore, process techniques to improve printability for some of the weak spots as applied to 65nm reticle sets will be discussed. An integrated scheme aiming at optimization of design rules and process rules is proposed.

关键词： model-based OPC systematic defects process rules 65nm node DFM dummy metal fill design rules full-chip simulation BEOL

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65nm OPC and design optimization by using simple electrical transistor simulation

65nm OPC and design optimization by using simple electrical ...

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conference on design and process integration for microelectronic manufacturing iii

作者： Trouiller, Y Devoivre, T Belledent, M Foussadier, F Borjon, A Patterson, K Lucas, K Couderc, C Sundermann, F Urbani, JC Baron, S Rody, Y Chapon, JD Arnaud, F Entradas, J CEA LETI F-38054 Grenoble France

ISBN: (纸本)0819457361

In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [ 1,2]. This study uses the following sequence to estimate the impact on transistor performance: 1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects. 2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis. rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples: design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor. Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.

关键词： design lithography OPC DFM gate 65nm

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