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检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration"

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2nd International conference on Electronic Commerce and Web Technologies, EC-Web 2001

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2nd International conference on Electronic Commerce and Web Technologies, EC-Web 2001

ISBN: (纸本)3540425179

The proceedings contain 32 papers. The special focus in this conference is on Web Software Development and XML Transformation. The topics include: An object-oriented approach to automate web applications development;tools for the design of user friendly web applications;an E-commerce based process model for cooperative software development in small organisations;extracting object-oriented database schemas from XML DTDs using inheritance;creating XML documents from relational data sources;composition of XML-transformations;classification and characteristics of electronic payment systems;an E-check framework for electronic payment systems in the web based environment;trader-supported information markets;an integrated framework of business models for guiding electronic commerce applications and case studies;models and protocol structures for software agent based complex E-commerce transactions;a multidimensional approach for modelling and supporting adaptive hypermedia systems;modelling the ICE standard with a formal language for information commerce;managing web data through views;applied information security for m-commerce and digital television environments;flexible authentication with multiple domains of electronic commerce;an asymmetric traceability scheme for copyright protection without trust assumptions;an application architecture for supporting interactive bilateral electronic negotiations;strategies for software agent based multiple issue negotiations;automatic construction of online catalog topologies;a two-layered integration approach for product information in B2B E-commerce;a visual one-page catalog interface for analytical product selection;engineering high performance database-driven E-commerce web sites through dynamic content caching and XML enabled metamodeling and tools for cooperative information systems.

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VLSI implementation of Mallat's fast discrete wavelet transform algorithm with reduced complexity

VLSI implementation of Mallat's fast discrete wavelet transf...

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IEEE conference and Exhibition on Global Telecommunications (GLOBECOM)

作者： Yuanbin Guo Hongzhong Zhang Xuguang Wang J.R. Cavallaro ECE Rice University Houston TX USA

This paper proposes a novel VLSI architecture to compute the DWT (discrete wavelet transform) coefficients using Mallat's algorithm with reduced complexity. We studied the commonality embedded in the mirror low-pass and high-pass filters of the algorithm and use a PLA as an address generator (PAG) to load the data for cascaded FIR computation. By using an embedded downsampling process in the control signal design, we reduced the complexity by saving storage and computation. The prototyping design is implemented and fabricated using the AMI 1.5 micron CMOS process through the MOSIS service.

关键词： Discrete wavelet transforms Very large scale integration Finite impulse response filter Embedded computing Computer architecture Mirrors Low pass filters Programmable logic arrays process control Signal design

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Cross-course design projects for engineering technology students

Cross-course design projects for engineering technology stud...

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Frontiers in Education (FIE) conference

作者： J.L. Newcomer Engineering Technology Department Western Washington University Bellingham WA USA

This paper describes how two classes in the Engineering Technology Department at Western Washington University, Applied Engineering Statics and Strength of Materials, have been linked together through the use of an integrated cross-course design project. The primary purpose of the project is to help students learn to utilize course material to analyze open-ended problems. In addition, various aspects of the project provide students with instruction and experience in project management, teamwork, oral, written and visual communication, creative problem solving, and business skills. Along with the goals and integration process, this paper describes the projects that have been used and the changes that have occurred. Assessment data shows that the integration of the project has been successful at meeting its goals.

关键词： design engineering Educational technology Positron emission tomography Automotive engineering Project management Teamwork Visual communication Problem-solving Plastics Electronics industry

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Adaptive array beamforming with fixed-point arithmetic matrix inversion using Givens rotations

Adaptive array beamforming with fixed-point arithmetic matri...

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conference on Advanced Signal processing Algorithms, Architectures, and Implementations XI

作者： Rabinkin, DV Song, W Vai, MM Nguyen, H MIT Lincoln Lab Lexington MA 02420 USA

ISBN: (纸本)0819441880

Adaptive array systems require the periodic solution of the well-known w = (R) over tilde (-1)v equation in order to compute optimum adaptive array weights. The covariance matrix (R) over tilde is estimated by forming a product of noise sample matrices X : (R) over tilde = (XX)-X-H. The operations-count cost of performing the required matrix inversion in real time can be prohibitively high for a high bandwidth system with a large number of sensors. Specialized hardware may be required to execute the requisite computations in real time. The choice of algorithm to perform these computations must be considered in conjunction with the hardware technology used to implement the computation engine. A systolic architecture implementation of the Givens rotation method for matrix inversion was selected to perform adaptive weight computation. The bit-level systolic approach enables a simple ASIC design and a very low power implementation. The bit-level systolic architecture must be implemented with fixed-point arithmetic to simplify the propagation of data through the computation cells. The Givens rotation approach has a highly parallel implementation and is ideally suited for a systolic implementation. Additionally, the adaptive weights are computed directly from the sample matrix X in the voltage domain, thus reducing the required dynamic range needed in carrying out the computations. An analysis was performed to determine the required fixed-point precision needed to compute the weights for an adaptive array system operating in the presence of interference. Based on the analysis results. it was determined that the precision of a floating-point computation can be well approximated with a 13-bit to 19-bit word length fixed point computation for typical system jammer-to-noise levels. This property has produced an order-of-magnitude reduction in required hardware complexity. A synthesis-based ASIC design process was used to generate preliminary layouts. These layouts were used t

关键词： Very large scale integration Chemical elements Computing systems Sensors Statistical analysis Computer architecture Matrices Radar Electroluminescence Signal processing

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Evaluation and optimization of package processing, design, and reliability through solder joint profile prediction

Evaluation and optimization of package processing, design, a...

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Electronic Components and Technology conference (ECTC)

作者： B.H. Yeung T.-Y.T. Lee Interconnect Systems Laboratories Motorola Inc. Tempe AZ USA

ISBN: (纸本)0780370384

Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.

关键词： design optimization process design Wafer scale integration Soldering Shape Assembly Chip scale packaging Application software Analytical models Software packages

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Towards an open architecture for the integration and interoperability of distributed systems

Towards an open architecture for the integration and interop...

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Enterprise Networking, Applications and Services conference Proceedings

作者： F.A. Rabhi School of Information Systems Technology and Management University of New South Wales Sydney Australia

This paper studies current developments and trends in the area of financial market systems. It investigates opportunities for the integration of existing and new services through a distributed software architecture and describes some of its essential features. It also discusses the development process of distributed applications based on the use of design patterns.

关键词： Computer architecture Software architecture Application software

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Intelligent decision support for protection scheme design associated with electrical transmission systems

Intelligent decision support for protection scheme design as...

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Power Industry Computer Application conference (PICA)

作者： G.M. West S.M. Strachan A. Moyes J.R. McDonald Centre for Electrical Power Engineering University of Strathclyde Glasgow UK

ISBN: (纸本)0780366816

This paper focuses on collaborative research activities conducted with two major UK utilities, describing the development of a web-based, design Engineering Knowledge Application System (DEKAS). This system offers automatic intelligent decision support to engineers responsible for the design and application of protection schemes associated with EHV transmission power systems. A web-based environment is promoted as the most effective medium for company-wide dissemination of the information and, knowledge captured within DEKAS. The paper also describes the integration of DEKAS with existing company data repositories in order to provide a single storage and retrieval mechanism for all pertinent information/documentation. Following the identification of 'what', 'where' and 'when' information and data are utilised within the overall protection design process, the paper then concentrates on 'how' better use can be made of existing engineering resources, through the development of an intelligent decision support facility, utilising case-base reasoning (CBR) techniques.

关键词： design engineering Knowledge engineering Documentation Power engineering and energy process design Data engineering Power system protection Collaboration Intelligent systems Information retrieval

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Modeling of hybrid supervisory systems using UML and Petri nets

Modeling of hybrid supervisory systems using UML and Petri n...

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International conference on Emerging Technologies and Factory Automation (ETFA)

作者： P. Eigi Miyagi E. Villani N. Maruyama Department Mechatronics-Esc. Politécnica Universidade de Sáo Paulo Sao Paulo Brazil

ISBN: (纸本)0780372417

In this work, a new approach for the design of supervisory systems is introduced. It focuses on how supervisory systems can improve global system performance through the use of efficient local controller switching configuration policies. For this purpose, a modeling approach is developed that can represent the integration of different hierarchical levels of the control architecture and different dynamic behavior. UML, Petri nets and differential equation systems are merged in order to provide a framework with flexibility for representing the abstractions that emerge when considering supervisory system design.

关键词： Unified modeling language Petri nets Control systems Mechatronics System performance Differential equations Three-term control Programmable control process design Control theory

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VLSI block placement using less flexibility first principles

VLSI block placement using less flexibility first principles

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Asia and South Pacific design Automation conference

作者： Sheqin Dong Xianlong Hong Youliang Wu Yizhou Lin Jun Gu Department of Computer Science and Technology Tsinghua University Beijing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong China Department of Computer Science Science and Technology University of Hong Kong Hong Kong China

ISBN: (纸本)0780366336

A deterministic algorithm for VLSI block placement was developed through human's accumulated experience in solving "packing" problem. Rectangle packing problem is just a simplified case of the polygon-shape stone plate packing problem that the ancient masons needed to face. Several "packing" principles derived from the so-called "less flexibility first" experience of the masons. A k-d tree data structure is used for manipulating the packed rectangles under the derived packing principles. Experiment results demonstrate that the algorithm is effective and promising in building block layout application.

关键词： Very large scale integration Computer science Tree data structures process design Humans Floors Wire

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PLC advanced technology demonstrator TestChipB

PLC advanced technology demonstrator TestChipB

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Custom Integrated Circuits conference (CICC)

作者： T. Vaida LSI Logic Corporation Boulder CO USA

ISBN: (纸本)0780365917

Rising complexity in ASIC Systems-On-Chip (SOC) has changed the nature of ASIC design and created a tremendous gap between the manufacturing capability and the engineering capability of ASIC designers and users. To solve this, LSI Logic has licensed the Programmable Logic Core (PLC) architecture developed by Adaptive Silicon Inc. This technology will allow ASIC designers to move some portions of the design later in the cycle, even as late as post tape-out. It will also allow for field reprogrammability. A simple test-chip TestChipA containing only the PLC was produced to verify the basic operation of the architecture. This device showed us that the architecture could be produced on an LSI process, but only exposed the physical design portions of the technology to testing. The next step is to develop a complete SOC device utilizing the PLC. This would enable us to rigorously test the methodologies, comb through the documentation and train our engineers to deliver a fully developed and well supported product. This paper describes the PLC architecture as well as the design methodologies needed to develop the test chip named TestChipB.

关键词： Programmable control Testing Application specific integrated circuits Large scale integration Programmable logic arrays Programmable logic devices Manufacturing design engineering Silicon Documentation

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