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检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration"

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Digital systems and electronics curricula proposal and tool integration

Digital systems and electronics curricula proposal and tool ...

引用

Frontiers in Education (FIE) conference

作者： M. Castra S. Acha J. Perez A. Hilario J.V. Miguez F. Mur F. Yeves J. Peire Dept. of Electr. & Comput. Eng. UNED Madrid Spain Engineering Department Burgos University Burgos Spain AlcoiE28099s Higher Polytechnic School Alcoy Spain Department of Electrical and Computer Engineering Universidad Nacional de Educacion a Distancia Madrid Spain

To transmit the teaching of digital electronics today, considerations are outlined which must be kept in mind. Digital electronics is evolving quickly and its techniques and tools have revolutionized the manner of analyzing simulating, synthesizing and verifying digital systems. Microelectronic development is more and more dependant on the technology and on design methodology. Standard hardware description languages (Verilog and VHDL), together with simulation and synthesis tools are some of the drivers behind microelectronic development. The "constructivist" model in the teaching-learning process proposes: significant learning as opposed to memorizing; structuring and sequencing of content; learning through guided discovery and a spiral or recurring procedure. These circumstances, together with pedagogical concern and the knowledge and experience that the authors have acquired as digital electronics teaching Professors have resulted in the formulation of a curricular proposal to transmit this updated teaching method. Using this teaching model as a base, the aim of the proposal is to have the student studying digital electronics acquire the theory and practices (know-how) from the beginning by using current design methodologies and CAD and EDA tools that the students will use in their professional future. Another objective of this method is to provide students with multimedia applications as a learning resource.

关键词： Digital systems Proposals Education Microelectronics design methodology Hardware design languages Analytical models Standards development Spirals design automation

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Hardware architecture for data concealment using sub-band coding, LSB coding and pseudo-random bit stream generators

Hardware architecture for data concealment using sub-band co...

引用

IEEE Region 10 International conference TENCON

作者： R.W. Adi C.M.M. Tio I. McLoughlin School of Computer Engineering Nanyang Technological University Singapore

Data concealment using sub-band LSB coding, LSB coding is an algorithm exhibiting good performance for hiding data within audio. This paper reports on the VLSI implementation techniques used for the algorithm. The implementation has both analogue input/output and digital audio input/output to interface to audio equipment, such as DAT, amplifier, audio precision analyser and similar. The architecture has been designed to give real time performance and consequently has high efficiency, whilst maintaining audio fidelity through careful analysis of wordlength and other effects. We also present the design study on investigating the feasibility of the selected implementation approach and estimate major system parameters.

关键词： Hardware Filters Computer architecture process design Data encapsulation Logic Clocks Data engineering Very large scale integration Performance analysis

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Limits of IT-driven knowledge management initiatives for interactive innovation processes: towards a community-based approach

Limits of IT-driven knowledge management initiatives for int...

引用

Annual Hawaii International conference on System Sciences (HICSS)

作者： J. Swan S. Newell M. Robertson Warwick Business School University of Warwick Coventry UK Nottingham Business School Nottingham Trent University Nottingham UK Coventry Business School Coventry University Coventry UK

ISBN: (纸本)0769504930

This paper begins with a critical review of the literature on Knowledge Management (KM), arguing that its focus on IT-based tools limits its potential for encouraging the knowledge sharing that is crucial to interactive innovation processes. Interactive innovation processes depend on the integration of knowledge across disparate social communities and require the exploration (creation) of knowledge, rather than simply the improved exploration of knowledge. Knowledge exploration depends on shared understanding, which is difficult where those involved are from different cultural and disciplinary bad grounds. In these situations, knowledge has to be continuously negotiated through interactive social networking processes. These processes are under-emphasised in most of the KM literature. Two cases of interactive innovation processes are presented. The contrast between these two cases leads to the development of two alternative approaches to KM: the community approach emphasises dialogue occurring through networks (which may be IT-enabled) while the cognitive approach emphasises linear information flows. It is argued that, at least in terms of encouraging interactive innovation processes, the community model is superior.

关键词： Knowledge management Technological innovation Best practices Context Innovation management Technology management Packaging Read only memory process design Business process re-engineering

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Materials challenges for wafer-level flip chip packaging

Materials challenges for wafer-level flip chip packaging

引用

Electronic Components and Technology conference (ECTC)

作者： Bodan Ma Q.K. Tong E. Zhan Sun Hee Hong A. Savoca National Starch and Chemical Company Bridgewater NJ USA

Flip chip as the smallest packaging design has been used in more and more electronic applications. Flip chip underfill is an essential component for the reliability of the package. Currently, the dispensing process is done at each individual chip level after interconnects have been made. The device then has to go through a separate curing process to harden the underfill material. This process is cumbersome and is one of the cost drivers of flip chip application. In wafer level flip chip packaging, the dispensing is made over the whole wafer in one step. After dicing, the reflow and the curing of underfill will be accomplished also in one step. The saving on process cost will be significant. The new process brings new challenges to underfill development. In addition to performing the reinforcement role as an underfill, these new materials have to act as a fluxing agent for solder reflow. They also have to have good room temperature stability after being dispensed onto wafer, handled at ambient environment, and before being cured in the reflow oven. The author will discuss parameters that determine the material performance at each processing step as well as the material development effort undergoing in a wafer-level underfill development program, which is sponsored by the Advanced Technology Program (ATP).

关键词： Flip chip Wafer scale integration Curing Electronics packaging Costs Semiconductor materials Temperature Cleaning Sun Chemicals

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integration strategies for smart power fast prototyping

Integration strategies for smart power fast prototyping

引用

conference Record of the IEEE Industry Applications Society Annual Meeting (IAS)

作者： A.P. Casimiro S. Finco P. Tavares F. Behrens M.I. Casto Simas Instituto Superior Técnico Fundação Centro Tecnológico para Informática Pontifícia Universidade Católica de Campinas Brazil

This paper presents a novel NMOS-based switching cell architecture specially developed for semicustom smart power ICs that can be implemented even using low cost, standard CMOS technologies. This approach is highly suitable either for cost effective smart power ICs or for discrete high power devices, since the NMOS transistor cell can be used to implement medium power switches or intermediate interface stages. This work also presents an overview on integration strategies and layout considerations, using different widely available processes of standard low cost CMOS technology, with no extra processing steps. Optimized NMOS devices were associated in special structures in a matrix arrangement, conveniently designed to be easily programmed using top metal masks, according to the required functionality, in order to implement topologies for commutation, drive, protection, amplification, sensing and control, capable to handle high voltage signals. The proposed power array allows the fast prototyping of a wide range of applications. As an example a therapeutic stimulation microsystem was obtained through the configuration of this power array fabricated using a standard CMOS technology. A boost converter was implemented as the actuator. Experimental results are presented and overall performance is discussed. These strategies can be extended to smart power and other power integration dedicated technologies, when customized ICs are in scope, to reduce low series production cost and production cycle.

关键词： Prototypes CMOS technology Costs Power integrated circuits Production Standards development MOSFETs CMOS process design optimization MOS devices

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One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications

One micron precision, wafer-level aligned bonding for interc...

引用

Electronic Components and Technology conference (ECTC)

作者： A.R. Mirza Electronic Visions Inc. Phoenix AZ USA

The ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate is becoming a critical issue for a variety of semiconductor applications. For CMOS devices this technology will be applied for chip-scale packaging and also for advanced 3-D interconnect processes. In the microelectromechanical systems (MEMS) arena, accurate alignment of two silicon micromachined wafers enables the design of more advanced MEMS devices and aggressive die shrinks of existing products. In this paper we discuss the advantages and disadvantages of various substrate-to-substrate alignment techniques including infrared, through wafer via, inter-substrate optical and wafer backside alignment methods. We also report on a new approach to wafer-to-wafer alignment that relies on precision alignment positioning systems to register and align wafers with one micron or better precision. Test results from this wafer-to-wafer alignment system demonstrate that one micron alignment accuracy can be routinely obtained. This new wafer-level alignment and bonding technique is particularly well suited for high-volume manufacturing due to the long-term stability of the precision alignment positioning system. This paper gives a brief overview of some typical uses of aligned wafer-level bonding for chip-scale, 3-D interconnect and MEMS applications.

关键词： Wafer bonding Silicon CMOS technology Micromechanical devices Substrates CMOS process Chip scale packaging Semiconductor device packaging Wafer scale integration Microelectromechanical systems

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On-the-fly rendering of losslessly compressed irregular volume data

On-the-fly rendering of losslessly compressed irregular volu...

引用

IEEE conference on Visualization

作者： Chuan-Kai Yang T. Mitra Tzi-Cker Chiueh Department of Computer Science State University of New York Stony Brook Stony Brook NY USA

Very large irregular-grid data sets are represented as tetrahedral meshes and may incur significant disk I/O access overhead in the rendering process. An effective way to alleviate the disk I/O overhead associated with rendering a large tetrahedral mesh is to reduce the I/O bandwidth requirement through compression. Existing tetrahedral mesh compression algorithms focus only on compression efficiency and cannot be readily integrated into the mesh rendering process, and thus demand that a compressed tetrahedral mesh be decompressed before it can be rendered into a 2D image. This paper presents an integrated tetrahedral mesh compression and rendering algorithm called Gatun, which allows compressed tetrahedral meshes to be rendered incrementally as they are being decompressed, thus leading to an efficient irregular grid rendering pipeline. Both compression and rendering algorithms in Gatun exploit the same local connectivity information among adjacent tetrahedra, and thus can be tightly integrated into a unified implementation framework. Our tetrahedral compression algorithm is specifically designed to facilitate the integration with an irregular grid renderer without any compromise in compression efficiency. A unique performance advantage of Gatun is its ability to reduce the runtime memory footprint requirement by releasing memory allocated to tetrahedra as early as possible.

关键词： Rendering (computer graphics) Image coding Compression algorithms Bandwidth Algorithm design and analysis Streaming media Head Lead compounds Pipelines Chromium

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integration of factory simulation with TCAD process and device simulation within a total TCAD approach to DFM

Integration of factory simulation with TCAD process and devi...

引用

conference on process and Equipment Control in Microelectronic Manufacturing

作者： Nilsen, VK Walton, AJ Univ Edinburgh Dept Elect & Elect Engn Edinburgh Midlothian Scotland

ISBN: (纸本)0819432229

This paper describes the integration of TCAD and factory simulation software tools to help facilitate their adoption as an integral part of a DFM (design for manufacturability) strategy. Automated exchange of data enables the impact on manufacturing operations to be more readily considered at an earlier stage during the process design procedure. The paper describes the design and operation of the FASTT (FActory Simulation in Total TCAD) software which integrates two commercially available simulation tools - TWB and ManSim/X. Two examples are used to illustrate its application within a DFM strategy.

关键词： FASTT total TCAD TCAD fcatory simulation DFM

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Incorporating process planning into conceptual design

Incorporating process planning into conceptual design

引用

ASME 1999 design Engineering Technical conferences, DETC 1999

作者： Feng, Shaw C. Nederbragt, Walter W. Kaing, Serge Shram, Ram D. Manufacturing Engineering Laboratory National Institute of Standards and Technology 100 Bureau Drive Stop 8260 GaithersburgMD20899-8260 United States

ISBN: (纸本)9780791819746

This paper describes recent developments in the design and process Planning integration (DPPI) project at the National Institute of Standards and Technology (NIST). The project addresses the need for improved communication between design and process planning in the early product design stage. Since major manufacturing costs are committed during product specification and design, it is critical to successfully assess manufacturability and cost as early as possible in the design process. Documenting the DPPI foundation, this paper reviews industry needs for an integrated design and manufacturing environment for rapid product development. Additionally, this paper describes the project's approach and the current status. Conceptual design and process planning prototype systems, that have been implemented, are also described. Finally, it describes the future direction for developing mechanisms to enable the integration of design and process planning, including information models and language interface specifications. Copyright © by 1999 ASME.

关键词： Conceptual design

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design for reliability in flip chip applications

Design for reliability in flip chip applications

引用

1999 International conference on High Density Packaging and MCMs

作者： Leal, J Yang, H Neathway, P Flip Chip Technol Phoenix AZ 85034 USA

ISBN: (纸本)0930815572

With growing interest in flip chip packaging as the premier interconnect solution, there is an urgent need for a system solution for flip chip applications. The successful implementation of flip chip packaging is dependent on the ability to design the integrated circuit (IC) for the flip chip. Although it is feasible to flip chip bump an IC designed for wirebonding, the ability to design the IC for flip chip increases its manufacturability and reliability from the bumping operation through assembly. From a total system perspective, the material selection and design aspects of board technology, underfill material, and assembly process also play vital roles in the flip chip application. This paper will focus on the basic design rules required for flip chip bumping, the impact of these design rules on bumping the wafer, and the resultant reliability of the device after assembly. The impact of substrate design and the assembly process on flip chip package reliability will also be discussed.

关键词： flip chip FCOB DCA solder bump eutectic Sn/Pb solder joint reliability

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