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检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration IV"

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Pattern Scaling with Directed Self Assembly through Lithography and Etch process integration

Pattern Scaling with Directed Self Assembly Through Lithogra...

引用

conference on Alternative Lithographic Technologies iv

作者： Rathsack, Benjamen Somervell, Mark Hooge, Josh Muramatsu, Makato Tanouchi, Keiji Kitano, Takahiro Nishimura, Eiichi Yatsuda, Koichi Nagahara, Seiji Hiroyuki, Iwaki Akai, Keiji Hayakawa, Takashi Tokyo Electron Amer Inc 2400 Grove Blvd Austin TX 78741 USA Tokyo Electron Kyushu Ltd Koshi Kumamoto 8611116 Japan Tokyo Electron Miyagi Ltd Nirasaki City Yamanashi 4070192 Japan Tokyo Electron Ltd Minato Ku Tokyo 1076325 Japan

ISBN: (纸本)9780819489791

Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards line edge roughness (LER) and pattern collapse improvement [1-4]. The current challenges for industry adoption are materials maturity, practical process integration, hardware capability, defect reduction and design integration. Tokyo Electron (TEL) has created close collaborations with customers, consortia and material suppliers to address these challenges with the long term goal of robust manufacturability. This paper provides a wide range of DSA demonstrations to accommodate different device applications. In collaboration with IMEC, directed line/space patterns at 12.5 and 14 nm HP are demonstrated with PS-b-PMMA (poly(styrene-b-methylmethacrylate)) using both chemo and grapho-epitaxy process flows. Pre-pattern exposure latitudes of >25% (max) have been demonstrated with 4X directed self-assembly on 300 mm wafers for both the lift off and etch guide chemo-epitaxy process flows. Within TEL's Technology Development Center (TDC), directed self-assembly processes have been applied to holes for both CD shrink and variation reduction. Using a PS-b-PMMA hole shrink process, negative tone developed pre-pattern holes are reduced to below 30 nm with critical dimension uniformity (CDU) of 0.9 nm (3 sigma) and contact edge roughness (CER) of 0.8 nm (3 sigma). To generate higher resolution beyond a PS-b-PMMA system, a high chi (chi) material is used to demonstrate 9 nm HP line/space post-etch patterns. In this paper, TEL presents process solutions for both line/space and hole DSA process integrations.

关键词： directed self-assembly (DSA) block copolymer double patterning pitch multiplication hole shrink anneal bake

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Manufacturing process Planning in Set-Based Concurrent Engineering Paradigm

Manufacturing Process Planning in Set-Based Concurrent Engin...

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9th IFIP WG 5.1 International conference on Product Lifecycle Management (PLM)

作者： Kerga, Endris Taisch, Marco Terzi, Sergio Politecn Milan Dept Econ Management & Ind Engn I-20133 Milan Italy Univ Bergamo Dept Ind Engn I-24044 Dalmine BG Italy

ISBN: (纸本)9783642357589

The integration of manufacturing planning activities into early design decisions is paramount. Manufacturing constraints and opportunities should be investigated early in a product development (PD) stages to launch products successfully. Set-based concurrent engineering (SBCE) paradigm is pronounced in literature and believed to form the foundation of lean thinking in PD. In SBCE, alternative product-subsystems are explored simultaneously and weak design choices are progressively eliminated as more knowledge about manufacturability becomes known. However, there is a methodological gap on how to execute SBCE in practice and integrate manufacturing process planning. This paper aims at conceptualizing the requirements to start manufacturing planning in the realm of SBCE paradigm. At the same time, the paper proposes a dialogue mechanism through which designers and manufacturing process planners are able to explore and evaluate alternative conceptual designs and process plans in parallel. Moreover, the methodology enables design and process knowledge to be effectively integrated for a better decision making.

关键词： Product Development (PD) Set-Based Concurrent Engineering (SBCE) Manufacturing process Planning

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Enhancing Overall System Functionality and Performance with the Right Packaging Solutions

Enhancing Overall System Functionality and Performance with ...

引用

13th International conference on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP)

作者： Karim, Nozad Zou, Yida Wen, Shengmin Amkor Technol Inc 1900 South Price Rd Chandler AZ 85286 USA

ISBN: (纸本)9781467316811;9781467316828

Printed circuit boards (PCBs) are the essential parts to assemble modern electronic circuits. The PCB design and development process has a direct impact on the system cost and time to market. On average, companies report that PCB represents 31% of the overall product cost. Today's electronic circuits and PCB designs are extremely complex. Multi-level mistakes are inevitable during the design and development stages. Cost reduction pressure is also limiting the designers in achieving their goals by reducing a few layers from their PCB stackup or adjusting and tweaking their designs. A paradigm shift in PCB design is underway through partitioning and modularizing the system and circuits to reduce PCB size and complexity, shortens design to market time, and simplifies the overall supply chain. In order to develop a superior product to fulfill a desired functions, good balance needs to be achieved among competing factors such as performance, cost, form factors, manufacturability, design, system flexibility, and supply chain management (Fig 1). A wireless system is usually comprised of several subsystems performing different functions. For example, a typical handset system includes baseband, transceivers, main and diversity FEM, memories, power management, power amplifiers, antenna switch, duplexer filter, etc. In this day and age, system integration is mandatory in order for end use products to offer superior and competitive products Compared to an SoC solution, system level integration at the packaging level may provide benefits such as cost effectiveness, flexibility, and a shorter development cycle. A concurrent development methodology between device and package design will definitely help the industry to understand the nature of system integration on a package

关键词： wireless system SiP System-in-Package Module System integration system size reductions copper pillar packaging solutions system cost reduction PoP TMV conformal shielding Integrated Packaging Device (IPD) 3D packaging 2.5D packaging

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Enhancing Overall System Functionality and Performance with the Right Packaging Solutions

Enhancing Overall System Functionality and Performance with ...

引用

2012 International conference on Electronic Packaging Technology & Hiigh Pachaging(2012电子封装和高密度封装国际会议(ICEPT-HDP2012))

作者： Shengmin Wen Nozad Karim Yida Zou Amkor Technology Inc.1900 South Price RoadChandlerAZ 85286USA Amkor Technology Inc.No.111 Yonglun RoadWigaoqiao Free Trade ZonePudongShanghai200131

Printed circuit boards (PCBs) are the essential parts to assemble modern electronic *** PCB design and development process has a direct impact on the system cost and time to *** average,companies report that PCB represents 31% of the overall product ***’s electronic circuits and PCB designs are extremely ***-level mistakes are inevitable during the design and development *** reduction pressure is also limiting the designers in achieving their goals by reducing a few layers from their PCB stackup or adjusting and tweaking their designs.A paradigm shift in PCB design is underway through partitioning and modularizing the system and circuits to reduce PCB size and complexity,shortens design to market time,and simplifies the overall supply *** order to develop a superior product to fulfill a desired functions,good balance needs to be achieved among competing factors such as performance,cost,form factors,manufacturability,design,system flexibility,and supply chain management (Fig 1).A wireless system is usually comprised of several subsystems performing different *** example,a typical handset system includes baseband,transceivers,main and diversity FEM,memories,power management,power amplifiers,antenna switch,duplexer filter,*** this day and age,system integration is mandatory in order for end use products to offer superior and competitive products Compared to an SoC solution,system level integration at the packaging level may provide benefits such as cost effectiveness,flexibility,and a shorter development cycle.A concurrent development methodology between device and package design will definitely help the industry to understand the nature of system integration on a package.

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Accurately Predicting Copper Interconnect Topographies in Foundry design for manufacturability Flows

Accurately Predicting Copper Interconnect Topographies in Fo...

引用

conference on design for manufacturability through design-process integration V

作者： Lu, Daniel Fan, Zhong Tak, Ki Duk Chang, Li-Fu Zou, Elain Jian, Jenny Yang, Josh Zhuang, Linda Chen, Kuang Han Hurat, Philippe Ding, Hua Semicond Mfg Int Corp Pudong New Area 18 Zhangjian Rd Shanghai 201203 Peoples R China Cadence Design Syst Inc San Jose CA 95134 USA Cadense Design Syst Inc Shanghai Peoples R China

ISBN: (纸本)9780819485335

This paper presents a model-based Chemical Mechanical Polishing (CMP) design for manufacturability (DFM) () methodology that includes an accurate prediction of post-CMP copper interconnect topographies at the advanced process technology nodes. Using procedures of extensive model calibration and validation, the CMP process model accurately predicts post-CMP dimensions, such as erosion, dishing, and copper thickness with excellent correlation to silicon measurements. This methodology provides an efficient DFM flow to detect and fix physical manufacturing hotspots related to copper pooling and Depth of Focus (DOF) failures at both block-and full chip level designs. Moreover, the predicted thickness output is used in the CMP-aware RC extraction and Timing analysis flows for better understanding of performance yield and timing impact. In addition, the CMP model can be applied to the verification of model-based dummy fill flows.

关键词： Chemical Mechanical Polishing (CMP) design for manufacturability (DFM) Physical hotspots Thickness Variation

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Moore's Law in the Innovation Era

Moore's Law in the Innovation Era

引用

conference on design for manufacturability through design-process integration V

作者： Bohr, Mark Intel Corp Logic Technol Dev Hillsboro OR 97124 USA

ISBN: (纸本)9780819485335

Traditional transistor scaling methods served our industry well for more than three decades until the early 1990s when leakage current and active power constraints threatened to end the continued improvements provided by Moore's Law. The end of the traditional scaling era ushered in the beginning of the innovation era. process technology innovations such as strained silicon, high-k metal gate transistors, and copper + low-k interconnects have enabled continued performance improvements for scaled devices. Microprocessor design and architecture innovations such as multi-core designs combined with power gates were significant contributors to improved performance and improved power efficiency. Future computing products demand small form factors and long battery life that can be met through a combination of transistor innovation, System-on-Chip and System-in-Package integration techniques.

关键词： Scaling process Innovation Microprocessor Innovation System-on-Chip System-in-Package

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Methodology for balancing design and process tradeoffs for deep-subwavelength technologies

Methodology for balancing design and process tradeoffs for d...

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conference on design for manufacturability through design-process integration V

作者： Graur, Ioana Wagner, Tina Ryan, Deborah Chidambarrao, Dureseti Kumaraswamy, Anand Bickford, Jeanne Styduhar, Mark Wang, Lee IBM Corp Syst & Technol Grp Hopewell Jct NY 12533 USA IBM Corp ASIC Circuit Enablement Team Bangalore Karnataka India IBM Corp Syst & Technol Grp Essex Jct VT 05452 USA

ISBN: (纸本)9780819485335

For process development of deep-subwavelength technologies, it has become accepted practice to use model-based simulation to predict systematic and parametric failures. Increasingly, these techniques are being used by designers to ensure layout manufacturability, as an alternative to, or complement to, restrictive design rules. The benefit of model-based simulation tools in the design environment is that manufacturability problems are addressed in a design-aware way by making appropriate trade-offs, e. g., between overall chip density and manufacturing cost and yield. The paper shows how library elements and the full ASIC design flow benefit from eliminating hot spots and improving design robustness early in the design cycle. It demonstrates a path to yield optimization and first time right designs implemented in leading edge technologies. The approach described herein identifies those areas in the design that could benefit from being fixed early, leading to design updates and avoiding later design churn by careful selection of design sensitivities. This paper shows how to achieve this goal by using simulation tools incorporating various models from sparse to rigorously physical, pattern detection and pattern matching, checking and validating failure thresholds.

关键词： OPC RET DR DFM simulation pattern recognition

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Decomposition-Aware Standard Cell design Flows to Enable Double-Patterning Technology

Decomposition-Aware Standard Cell Design Flows to Enable Dou...

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conference on design for manufacturability through design-process integration V

作者： Liebmann, Lars Pietromonaco, David Graf, Matthew IBM Corp Hopewell Jct NY 12533 USA ARM San Jose CA USA IBM Corp Burlington VT USA

ISBN: (纸本)9780819485335

Maintaining the microelectronics industry's aggressive pace of density scaling beyond the resolution limits of optical lithography is forcing the introduction of double-patterning technology (DPT) that effectively doubles the pattern density achievable with 193nm optical lithography. This paper investigates the degree to which DPT affects design tools, layout methodologies, and data standards. design solutions are demonstrated and the efficiency of various double-patterning aware design methodologies is compared based on the first metal level of a 20nm-node standard cell design flow. Necessary design-tool and data-standard requirements for a DPT-aware standard cell design flows are enumerated and summarized.

关键词： double-patterning technology (DPT) design rule checking (DRC) standard cell design placement routing

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Aerial Image Retargeting (AIR): Achieving Litho-Friendly designs

Aerial Image Retargeting (AIR): Achieving Litho-Friendly Des...

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conference on design for manufacturability through design-process integration V

作者： Hamouda, Ayman Yehia Word, James Anis, Mohab Karim, Karim S. Mentor Graphics Corp Wilsonville OR 97070 USA Univ Waterloo Dept ECE Waterloo ON N2L 3G1 Canada Amer Univ Dept ECE Cairo Egypt

ISBN: (纸本)9780819485335

In this work, we present a new technique to detect non-Litho-Friendly design areas based on their Aerial Image signature. The aerial image is calculated for the litho target (pre-OPC). This is followed by the fixing (retargeting) the design to achieve a litho friendly OPC target. This technique is applied and tested on 28 nm metal layer and shows a big improvement in the process window performance. For an optimized Aerial-Image-Retargeting (AIR) recipe is very computationally efficient and its runtime doesn't consume more than 1% of the OPC flow runtime.

关键词： OPC RET LFD DFM process window Model-based retargeting Aerial Image

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Rerouting and Guided Repair Strategies To Resolve Lithography Hotspots

Rerouting and Guided Repair Strategies To Resolve Lithograph...

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conference on design for manufacturability through design-process integration V

作者： Maerz, Reinhard Peter, Kai Engelhardt, Kay Infineon Technol Munich Germany

ISBN: (纸本)9780819485335

In contrast to defect limited yield loss, systematic yield detractors like lithography hotspots may cause a huge yield loss per event. For 45 nm and subsequent technology nodes, those findings are for this reason classified as DRC-like errors and need to be fixed before tape-out. In this paper, we report a comparison - from the use-model point-of-view - of two different methods for removal of lithography hotspots. First, a rip-up & re-routing and second, a guided-repair approach will be presented. This includes a discussion of the impact in the routing context, mainly radius of influence and timing closure, aspects of multiple layer involvement and the layout hierarchy, and the limitations caused by the layout grid.

关键词： design for manufacturing lithography friendly design re-routing guided repair

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