检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

307 篇 会议
3 篇 期刊文献

馆藏范围

310 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

255 篇 工学
- 140 篇 电气工程
- 124 篇 机械工程
- 49 篇 材料科学与工程（可...
- 27 篇 计算机科学与技术...
- 14 篇 软件工程
- 12 篇 电子科学与技术（可...
- 10 篇 控制科学与工程
- 5 篇 力学（可授工学、理...
- 5 篇 信息与通信工程
- 4 篇 化学工程与技术
- 3 篇 土木工程
- 3 篇 轻工技术与工程
- 2 篇 冶金工程
- 2 篇 航空宇航科学与技...
- 2 篇 生物医学工程（可授...
- 1 篇 光学工程
190 篇 理学
- 179 篇 物理学
- 8 篇 数学
- 4 篇 化学
- 3 篇 统计学（可授理学、...
- 2 篇 生物学
- 1 篇 天文学
- 1 篇 系统科学
22 篇 管理学
- 22 篇 管理科学与工程(可...
- 6 篇 工商管理
8 篇 教育学
- 8 篇 教育学
- 1 篇 心理学(可授教育学...
2 篇 医学
- 2 篇 临床医学
1 篇 经济学
- 1 篇 应用经济学
1 篇 法学
- 1 篇 社会学

主题

53 篇 dfm
50 篇 lithography
37 篇 opc
32 篇 design for manuf...
30 篇 manufacturing
27 篇 optical proximit...
25 篇 design for manuf...
19 篇 transistors
19 篇 silicon
17 篇 double patternin...
16 篇 photomasks
15 篇 design for manuf...
13 篇 process window
12 篇 design rule
11 篇 simulation
11 篇 hotspot
11 篇 data modeling
10 篇 yield
10 篇 ret
9 篇 double patternin...

机构

16 篇 cadence design s...
12 篇 mentor graph cor...
5 篇 synopsys inc aus...
5 篇 globalfoundries ...
4 篇 samsung elect co...
4 篇 carnegie mellon ...
4 篇 univ calif berke...
3 篇 ibm corp fishkil...
3 篇 appl mat inc san...
3 篇 mentor graph cor...
3 篇 mentor graphics ...
3 篇 natl univ singap...
3 篇 synopsys inc 700...
3 篇 clear shape tech...
3 篇 univ calif berke...
3 篇 toshiba co ltd s...
3 篇 zhejiang univ in...
3 篇 freescale semico...
3 篇 chartered semico...
3 篇 globalfoundries ...

作者

20 篇 hurat philippe
12 篇 capodieci luigi
10 篇 liebmann lars
8 篇 lucas kevin
8 篇 pileggi larry
8 篇 verghese nishath
6 篇 jhaveri tejas
5 篇 maeda shimon
5 篇 kye jongwook
5 篇 kim kee sup
5 篇 spanos costas j.
5 篇 kyoh suigen
5 篇 pan david z.
5 篇 inoue soichi
5 篇 ha naya
4 篇 strojwas andrzej
4 篇 mansfield scott
4 篇 neureuther andre...
4 篇 chao kai-yuan
4 篇 torres j. andres

语言

307 篇 英文
3 篇 其他

检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration IV"

共 310 条记录，以下是111-120 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Lithography Aware design Optimization using ILT

Lithography Aware Design Optimization using ILT

引用

conference on design for manufacturability through design-process integration V

作者： Jeong, Jaeyoon Jeong, Seokyun Ahn, Changhoon Jang, Yongsun Lee, Sukjoo Cecil, Thomas Son, Donghwan Chow, Tatung Kim, David Samsung Elect Co Ltd San 24 Yongin 445701 Gyeonggi Do South Korea Luminescent Technol Inc Palo Alto CA 94303 USA

ISBN: (纸本)9780819485335

For increasingly small and dense designs requiring adequate DOF, MEEF, and EL, numerous technologies have been employed to increase yield. Some techniques such as process optimization (i.e. SMO) are effective, but can be costly and time consuming, and are not easily modifiable once an initial choice is made. design optimization can be done separately from knowledge of the fab's OPC correction, but for sub 32nm nodes the complexity and interaction of the design target shapes is becoming too complicated for predefined design rules to produce an acceptable result. In this paper we introduce a method called Lithographically Enhanced Edge design (LEED) suited for IDMs. This joint target and mask optimization method takes into account the full OPC correction and process, and modifies the user's design in a controlled way so as to produce a new design with improved lithographic performance which can be used in place of the initial design. Control is given to the user so that inter-layer dependencies are not broken. Also, integrated target, mask, and source optimization is available in cases where target and mask optimization in not sufficient to produce adequate results. The use of ILT allows efficient target, mask, and source correction without extensive user OPC scripting and target modification sweeping. We show LEED results which enable production at 20x node.

关键词： DFM design Optimization Layout Optimization ILT OPC

来源：评论

学校读者我要写书评

暂无评论

Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device

Statistical approach to specify DPT process in terms of patt...

引用

conference on design for manufacturability through design-process integration V

作者： Pyo, Yu-Jin Choi, Soo-Han Park, Chul-Hong Lee, Sang-Hoon Yoo, Moon-Hyun Kim, Gyu-Tae Samsung Elect Co Ltd CAE Team Semicond R&D Ctr Seoul South Korea Korea Univ Sch Elect Engn Seoul South Korea

ISBN: (纸本)9780819485335

Double-patterning technology (DPT) has been a primary lithography candidate of the sub-30nm technology node. The major concern of DPT is the critical dimension (CD) skew and overlay error between 1st and 2nd patterning, which cause the degradation of the electrical performance in terms of timing delay. In this paper, we newly develop a systematic method to determine the DPT scheme and the proper process specification using a statistical approach in perspective of the pattering and electrical performance. Applying the method to the bit-line layer of the sub-30nm DRAM device, we determine the DPT scheme (i.e. either litho-etch-litho-etch (LELE) or self-aligned double pattering (SADP) to avoid the patterning hotspots. In addition, analyzing the statistical simulation result, we provide the process specification and exposing sequence of two masks to avoid the electrical degradation.

关键词： double patterning hotspot electrical performance process specification DRAM

来源：评论

学校读者我要写书评

暂无评论

Using Templates and Connectors for Layout Pattern Minimization in 20nm and Below Technology Nodes

Using Templates and Connectors for Layout Pattern Minimizati...

引用

conference on design for manufacturability through design-process integration V

作者： Jhaveri, Tejas K. Strojwas, Andrzej J. PDF Solut Pittsburgh PA 15232 USA

ISBN: (纸本)9780819485335

Layout pattern minimization has become a necessity at the 20nm technology node. Not only is it the only way to guarantee convergence for source mask optimization, having a well defined design space by limiting the total number of layout patterns, is the only way to ensure complete verification of design space during technology bring-up. In this paper we would reveal the details of PDF Solutions template and connector based layout design methodology that enables designers to achieve competitive layout density by limiting layout patterns. The use of this methodology enables a 25X pattern count reduction compared to the gridded logic layouts and is the only solution available that ensure pattern count saturation within a 40um x 40um random block of logic. Results on SMO compatibility have been highlighted by the collaborative work between ASML and PDF Solutions. In this paper we have discussed the development of a layout fabric developed for SMO and DPT compatibility, the definition of the base template and corresponding connector templates to provide the fabric constraints to designers and results highlighting the lithographic benefits of this approach. In effect, we have proposed a design solution that can provide a low-risk 20nm technology node enablement.

关键词： Templates Regular design Fabric Computational Lithography DFM SMO DPT

来源：评论

学校读者我要写书评

暂无评论

Characterization of the Performance Variation for Regular Standard Cell with process Nonidealities

Characterization of the Performance Variation for Regular St...

引用

conference on design for manufacturability through design-process integration V

作者： Zhang, Hongbo Du, Yuelin Wong, Martin D. F. Chao, Kai-Yuan Univ Illinois Dept ECE Urbana IL USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9780819485335

In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-D cell characterization shows that the timing variations can be characterized by the timing model.(1,2) However, as regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its advantages and has drawn intensive research interest. The circuit performance of a 1-D standard cell can be more accurately predicted than that of a 2-D standard cell as it is insensitive to layout context. This paper presents a characterization methodology to predict the delay and power performance of 1-D standard cells. We perform lithography simulation on the poly gate array generated by dense line printing technology, which constructs the poly gates of inverters, and do statistical analysis on the data simulated within the process window. After that, circuit simulation is performed on the printed cell to obtain its delay and power performance, and the delay and power distribution curves are generated, which accurately predict the circuit performance of standard cells. In the end, the benefits of our cell characterization method are analyzed from both design and manufacturing perspectives, which shows great advantages in accurate circuit analysis and yield improving.

关键词： 1-D Patterning Dense Line Printing Standard Cell Characterization

来源：评论

学校读者我要写书评

暂无评论

Standard Cell Electrical and Physical Variability Analysis based on Automatic Physical Measurement for design-for-Manufacturing Purposes

Standard Cell Electrical and Physical Variability Analysis b...

引用

conference on design for manufacturability through design-process integration V

作者： Shauly, Eitan Parag, Allon Khmaisy, Hafez Krispil, Uri Adan, Ofer Levi, Shimon Latinsky, Sergey Schwarzband, Ishai Rotsteina, Israel Tower Semicond LTD POB 619 IL-23105 Migdal Ha Emek Israel Mentor Graph Corp IL-46120 Hertzelia Israel Technion Israel Inst Technol Dept Mat Engn IL-32000 Haifa Israel Appl Mat Inc IL-76705 Rehovot Israel

ISBN: (纸本)9780819485335

A fully automated system for process variability analysis of high density standard cell was developed. The system consists of layout analysis with device mapping: device type, location, configuration and more. The mapping step was created by a simple DRC run-set. This database was then used as an input for choosing locations for SEM images and for specific layout parameter extraction, used by SPICE simulation. This method was used to analyze large arrays of standard cell blocks, manufactured using Tower TS013LV (Low Voltage for high-speed applications) Platforms. Variability of different physical parameters like and like Lgate, Line-width-roughness and more as well as of electrical parameters like drive current (Ion), off current (Ioff) were calculated and statistically analyzed, in order to understand the variability root cause. Comparison between transistors having the same W/L but with different layout configurations and different layout environments (around the transistor) was made in terms of performances as well as process variability. We successfully defined "robust" and "less-robust" transistors configurations, and updated guidelines for design-for-Manufacturing (DfM).

关键词： Transistors Ions Scanning electron microscopy Device simulation Semiconducting wafers Silicon Statistical analysis design for manufacturing Electrochemical etching Optical proximity correction

来源：评论

学校读者我要写书评

暂无评论

Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks

Extending analog design scaling to sub-wavelength lithograph...

引用

conference on design for manufacturability through design-process integration V

作者： Parikh, Ashesh Dorris, Siew Smelko, Tom Walbrick, Walter Mahalingam, Pushpa Arch, John Green, Kent Garg, Vishal Buck, Peter West, Craig Texas Instruments Inc MS 36613121 TI Blvd Dallas TX 75243 USA Toppan Photomasks Round Rock TX 78664 USA

ISBN: (纸本)9780819485335

The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle time. design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer needs but still manage the computational lithography overhead as well as the patterning process performance, this process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems, comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary to switch to the new mask process were analyzed.

关键词： optical proximity correction (OPC) resolution enhancement technologies (RET) reticles mask writer 50KeV vector writer deep ultra-violet (DUV) laser writer

来源：评论

学校读者我要写书评

暂无评论

Multi-selection method for physical design verification applications

Multi-selection method for physical design verification appl...

引用

conference on design for manufacturability through design-process integration V

作者： Mostafa, Salma Torres, J. Andres Rezk, Peter Madkour, Kareem Mentor Graph Egypt 78 El Nozha St Cairo 11361 Egypt Mentor Graph Corp Wilsonville OR 97070 USA

ISBN: (纸本)9780819485335

In this paper we present a modular approach which combines model based verification, pattern matching and machine learning methods in order to achieve a high accuracy over computing time ratio. We utilize pattern recognition technique using a supervised machine learning system (as opposed to pattern matching) to classify the patterns either as failures (hotspots) or non-failures, and we use pattern matching to detect all the outlier misses and false detections in each of the regions (based on the calibration set), which will be added or removed from the set of hotspots later on. Doing so allows us to do two things: Reduce the number of patterns that need to be pattern matched since only the outliers of the machine learning system need to be considered and more importantly it allows us to add trained predictability to new configurations that were not in the training set but that can be interpolated from the system. The results indicate that indeed it is possible to successfully combine Machine learning with pattern matching methods in order to achieve better predictability of errors of previously unseen data, while being exact in the treatment of previously observed data. We also explore possible avenues to further speed up the computation of the layout characterization process by inserting a global density grid, and assess the impact of model quality and aliasing under real detection conditions.

关键词： DFM Lithography checks layout verification layout portability layout compatibility

来源：评论

学校读者我要写书评

暂无评论

A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation

A state-of-the-art hotspot recognition system for full chip ...

引用

conference on design for manufacturability through design-process integration V

作者： Simmons, Mark C. Kang, Jae-hyun Kim, Youngkeun Park, Joung Il Paek, Seung Weon Kim, Kee-sup Mentor Graphics Corp. (United States) SAMSUNG Electronics Co. Ltd. (Korea Republic of) Mentor Korea Co. Ltd. (Korea Republic of)

ISBN: (纸本)9780819485335

In today's semiconductor industry, prior to wafer fabrication, it has become a desirable practice to scan layout designs for lithography-induced defects using advanced process window simulations in conjunction with corresponding manufacturing checks. This methodology has been proven to provide the highest level of accuracy when correlating systematic defects found on the wafer with those identified through simulation. To date, when directly applying this methodology at the full chip level, there has been unfavorable expenses incurred that are associated with simulation which are currently overshadowing its primary benefit of accuracy - namely, long runtimes and the requirement for an abundance of cpus. Considering the aforementioned, the industry has begun to lean towards a more practical application for hotspot identification that revolves around topological pattern recognition in an attempt to sidestep the simulation runtime. This solution can be much less costly when weighing against the negative runtime overhead of simulation. The apparent benefits of pattern matching are, however, counterbalanced with a fundamental concern regarding detection accuracy;topological pattern identification can only detect polygonal configurations, or some derivative of a configuration, which have been previously identified. It is evident that both systems have their strengths and their weaknesses, and that one system's strength is the other's weakness, and vice-versa. A novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation will be introduced. This system will attempt to minimize the negative aspects of both pattern matching and simulation. The proposed methodology has a high potential to decrease the amount of processing time spent during simulation, to relax the high cpu count requirement, and to maximize pattern matching accuracy by incorporating a multi-staged pattern matching flow prior to performing simulation on a reduced dat

关键词： candidate hotspot coldspot hotspot lithography pattern matching process window semiconductor

来源：评论

学校读者我要写书评

暂无评论

The effective etch process proximity correction methodology for improving on chip CD variation in 20 nm node DRAM gate

The effective etch process proximity correction methodology ...

引用

conference on design for manufacturability through design-process integration V

作者： Park, Jeong-Geun Kim, Sang-Wook Shim, Seong-Bo Suh, Sung-Soo Oh, Hye-Keun Hanyang Univ Dept Appl Phys Ansan 426791 Gyeonggi Do South Korea Samsung Elect CO LTD Semicond R&D Ctr CTP OPC Proc Dev Team Hwasung 445701 Gyeonggi Do South Korea

ISBN: (纸本)9780819485335

This paper presents an effective methodology for etch PPC (process Proximity Correction) of 20 nm node DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation) control become more important to meet the performance goal for high speed in DRAM. The main factors which influence OCV are mask, photo, etch PPE (process proximity effect) in DRAM gate. Model based etch PPC is required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density difference between spider mask and real gate mask, the skew difference occurs between them. We tested the effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 similar to 10 mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm). This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce this skew difference between spider mask and real mask, we applied open field mask correction term and long range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up to 67%.

关键词： process proximity correction on chip CD variation dynamic random access memory gate etch long range density effect

来源：评论

学校读者我要写书评

暂无评论

design for manufacturability through design-process integration iv

Design for Manufacturability through Design-Process Integrat...

引用

design for manufacturability through design-process integration iv

ISBN: (纸本)9780819480552

The proceedings contain 36 papers. The topics discussed include: application of the cost-per-good-die metric for process design co-optimization;taming the final frontier of optical lithography: design for sub-resolution patterning;layout pattern minimization for next-generation technologies;exploring complex 2D layouts for 22nm node using double patterning/double etch approach for trench levels;systematic failure debug and defective pattern extraction for FPGA product yield improvement;modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell;variability aware timing models at the standard cell level;45nm-generation parameter-specific ring oscillator monitors;DRCPlus in a router: automatic elimination of lithography hotspots using 2D pattern detection and correction;and using a highly accurate self-stop Cu-CMP model in the design flow.

关键词：

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共31页 << < 8 9 10 11 12 13 14 15 16 17 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：