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检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration IV"

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SRAM Circuit Performance in the Presence of process Variability of Self-aligned Multiple Patterning

SRAM Circuit Performance in the Presence of Process Variabil...

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conference on design for manufacturability through design-process integration VII

作者： Xiao, Wei Cheng, Qi Chen, Yijian Peking Univ Sch Elect & Comp Engn Shenzhen Grad Sch Shenzhen 518055 Guangdong Peoples R China

ISBN: (纸本)9780819494665

The impacts of self-aligned triple patterning (SATP) and self-aligned quadruple patterning (SAQP) process variability on SRAM circuit performance are studied in this paper. Different types of SRAM circuit variability such as intra-cell and inter-cell variability are discussed. Spatially periodic variation patterns of a SRAM array fabricated with SATP process is identified, while spatial variation of SAQP based SRAM array is found to be less significant. Statistical TCAD simulations are carried out to examine the process variability induced fluctuation of SRAM circuit performance. It is found that SRAM static noise margin (SNM) shrinks with increased variations in line-width roughness and CD, especially when the technology node is scaled down. Despite the SATP/SAQP process variability and the related SNM reduction, our simulations show that the induced fluctuation of SRAM circuits is still manageable. It is also confirmed that circuit stability and manufacturing yield of SAQP based SRAM are better than SATP based SRAM.

关键词： Self-aligned triple patterning (SATP) self-aligned quadruple patterning (SAQP) SRAM static noise margin (SNM) inter-cell variability intra-cell variability

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Pioneering an On-The-Fly Simulation Technique for the Detection of Layout-Dependent Effects during IC design Phase

Pioneering an On-The-Fly Simulation Technique for the Detect...

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conference on design for manufacturability through design-process integration VII

作者： Tosson, Amr M. S. Ramadan, Ahmed Salem, Rami Fathy Mentor Graphics Egypt (Egypt) Mentor Graphics Corp. (Canada)

ISBN: (纸本)9780819494665

As semiconductor manufacturing migrates to more advanced technology nodes, the performance improvement anticipated from scaling has failed to match expectations. This failure is due to the emergence of layout-dependent effects (LDEs) not encountered in the design flow prior 65nm process node. We propose a novel methodology that allows the early detection of LDEs during schematic creation. Different from all previous works, this methodology accurately calculates LDEs by interfacing interactively with a simulator tool. Our research indicates that no previous works suggested the use of "on-the-fly" simulation, using Eldo Interactive, to study LDEs. In fact, the use of Calibre tools [2] has been suggested to help the designer check certain basic electrical constraints (like matching) under the existence of LDEs, by specifying the matching condition as a comment added to the original Pyxis schematic netlist. [1] These comments are then transformed into verification rules that are added and checked by Calibre. The proposed flow is tested on a 40nm OTA design, with results not only as accurate as those previously obtained from post-layout analysis, but also equal to or better speed of execution, demonstrating the practicality of using "on-thefly" simulation to detect and resolve LDEs early in the design flow.

关键词： Device simulation Molybdenum Transistors Field effect transistors Manufacturing Semiconductor manufacturing Visualization Integrated circuits Scattering Semiconductors

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design for manufacturability through design-process integration VII

Design for Manufacturability through Design-Process Integrat...

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SPIE conference on designfor manufacturability through design-process integration, DfM-DPI 2013

ISBN: (纸本)9780819494665

The proceedings contain 23 papers. The topics discussed include: diffraction pattern based optimization of lithographic targets for improved printability;self-aligned double patterning friendly configuration for standard cell library considering placement impact;evaluation of cost-driven triple patterning lithography decomposition;self-aligned double patterning compliant routing with in-design physical verification flow;pattern matching for identifying and resolving non-decomposition-friendly designs for double patterning technology (DPT);detailed routing with advanced flexibility and in compliance with self-aligned double patterning constraints;pioneering an on-the-fly simulation technique for the detection of layout-dependent effects during IC design phase;rethinking ASIC design with next generation lithography and process integration;enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification;mask strategy and layout decomposition for self-aligned quadruple patterning;and process characteristics and layout decomposition of self-aligned sextuple patterning.

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manufacturability Analysis of Integrated Product based on Feature Mapping

Manufacturability Analysis of Integrated Product based on Fe...

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3rd International conference on Applied Mechanics, Materials and Manufacturing (ICAMMM 2013)

作者： Tian, Jianping Huang, Danping Zhang, Liangdong Yang, Haili Huang, Yuchun Sichuan Univ Sci & Engn Sch Mech Engn Zigong 643000 Peoples R China

ISBN: (纸本)9783037858882

For the lack of effective product representation method, traditional CAD system cannot support integration of product design and manufacture effectively. This integration is the key to achieving Three-dimensional process design. Using the model definition of manufacturing feature, the part information of processing & manufacturing could be expressed completely. This representation method was put forward using the manufacturing feature of "cutting characteristics". A dynamic model of the manufacturing feature was established. through study on mapping rules between features, the shape features mapping to the manufacturing features were realized. An effective solving way was provided for the expression of CAPP product model.

关键词： feature mapping manufacturing feature manufacturability analysis integrated product

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process window analysis of algorithmic assist feature placement options at the 2X nm Node DRAM

Process window analysis of algorithmic assist feature placem...

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conference on design for manufacturability through design-process integration VII

作者： Jeon, Jinhyuck Kim, Shinyoung Song, Jookyoung Park, Chanha Yang, Hyunjo Yim, Donggyu Ward, Brian Zhang, Yunqiang Hooker, Kevin Do, Munhoe Choi, Jung-Hoe Jang, Stephen SK Hynix Semicond Inc Memory Res & Dev Div Seoul South Korea

ISBN: (纸本)9780819494665

As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits;subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. AF placement algorithms can be categorized broadly as either rule-based (RB), model-based (MB). However, combining these different algorithms into new integrated solutions may enable a more optimal overall solution. RBAF is the baseline AF placement method for many previous technology nodes. Although RBAF algorithm complexity limits its use with very extreme illumination, RBAF is still a powerful option in certain scenarios. One example is for repeating patterns in memory arrays. RBAF algorithms can be finely optimized and verified experimentally without the building of complex models. RBAF also guarantees AF placement consistency based only on the very local geometric environment, which is important in applications where consistent signal propagation is of critical importance. MBAF algorithms deliver the ability to reliably place assist features for enhanced process window control across a wide variety of layout feature configurations and aggressive illumination sources. These methods optimize sophisticated AF placement to improve main feature PW but without performing full main feature OPC. The flexibility of MBAF allows for efficient investigations of future technology nodes as the number of interactions between local layout features increases beyond what RBAF algorithms can effectively support Based on hybrid approach algorithms combining features of the different algorithms using both RBAF and MBAF methods, the generation and placement of SRAF can be a good alternative. Combining of two kinds of SRAF placement options might result in relatively improved process window compared to an independent

关键词： SRAF Atrial fibrillation Critical dimension metrology Optical proximity correction Semiconducting wafers Photomasks Model-based design Manufacturing Inspection Printing

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Advances in Directed Self Assembly integration and manufacturability at 300 mm

Advances in Directed Self Assembly Integration and Manufactu...

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conference on Advances in Resist Materials and processing Technology XXX

作者： Rathsack, Benjamen Somervell, Mark Muramatsu, Makato Tanouchi, Keiji Kitano, Takahiro Nishimura, Eiichi Yatsuda, Koichi Nagahara, Seiji Iwaki, Hiroyuki Akai, Keiji Ozawa, Mariko Negreira, Ainhoa Romo Tahara, Shigeru Nafus, Kathleen Tokyo Electron Amer Inc 2400 Grove Blvd Austin TX 78741 USA Tokyo Elect Kyushu Ltd Kumamoto 8611116 Japan Tokyo Elect Miyagi Ltd Nirasaki City Yamanashi 4070192 Japan Tokyo Elect Ltd Minato Ku Tokyo 107 Japan Tokyo Elect Ltd IMEC B-3001 Louvain Belgium

ISBN: (纸本)9780819494641

Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards LWR and pattern collapse improvement [1-10]. TEL has developed a DSA development ecosystem (collaboration with customers, consortia, inspection vendors and material suppliers) to successfully demonstrate directed PS-PMMA DSA patterns using chemo-epitaxy (lift-off and etch guide) and grapho-epitaxy integrations on 300 mm wafers. New processes are being developed to simplify process integration, to reduce defects and to address design integration challenges with the long term goal of robust manufacturability. For hole DSA applications, a wet development process has been developed that enables traditional post-develop metrology through the high selectivity removal of PMMA cylindrical cores. For line/space DSA applications, new track, cleans and etch processes have been developed to improve manufacturability. In collaboration with universities and consortia, fundamental process studies and simulations are used to drive process improvement and defect investigation. To extend DSA resolution beyond a PS-PMMA system, high chi materials and processes are also explored. In this paper, TEL's latest process solutions for both hole and line/space DSA process integrations are presented.

关键词： directed self-assembly block copolymer anneal bake double patterning

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NOVEL TPMS SENSING CHIP WITH PRESSURE SENSOR EMBEDDED IN ACCELEROMETER

NOVEL TPMS SENSING CHIP WITH PRESSURE SENSOR EMBEDDED IN ACC...

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International conference on Solid-State Sensors, Actuators and Microsystems

作者： W.-C. Yeh C.-K. Chan J. Hsieh C.-F. Hu F.-M. Hsu W. Fang Asia Pacific Microsystems Inc. Hsinchu TAIWAN Power Mechanical Eng. Dept. National Tsing Hua Univ. Hsinchu TAIWAN

ISBN: (纸本)9781467359825

This study reports the design architecture to embed piezoresistive pressure sensor into accelerometer (PinG sensor) on a single chip by using the cavity-SOI process. The monolithic sensing chip can find various applications such as tire pressure monitoring system (TPMS), etc. The merits of the presented design includes significant chip size reduction by integrating the diaphragm of pressure sensor into the proof-mass of accelerometer, as well as better manufacturability through combining piezoresistor (PZR) process and CSOI process. Preliminary tests demonstrated the feasibility of detecting both pressure and acceleration using the presented PinG sensor. This design architecture is also applicable for other sensors integration.

关键词： piezoresistive pressure sensor accelerometer combo sensor monolithic integration TPMS

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A primer of physical design for lithographers

A primer of physical design for lithographers

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Yuan, Chi-Min (Chi) Freescale Semicond Inc Phys Design & DFM Austin TX 78746 USA

ISBN: (纸本)9780819489838

In the SPIE Microlithography DFM conference, the number of papers related to physical design has been steadily increasing in the last few years. Since the majority of the audience in this conference has a background in lithographers, some of the physical design-related terminologies and method described in the presentations may be hard to understand. This paper gives a basic introducation the physical design that is applicable to lithographers. The goal of the paper is not to enable a lithographer to begin working as a physical designer. Instead, it is to help lithographers understand some of the basics of physical design, so that they can better comprehend other DFM papers presented at the conference.

关键词： physical design lithography

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Framework for Identifying Recommended Rules and DFM Scoring Model to Improve manufacturability of sub-20nm Layout design

Framework for Identifying Recommended Rules and DFM Scoring ...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Pathak, Piyush Madhavan, Sriram Malik, Shobhit Wang, Lynn T-N. Capodieci, Luigi GLOBALFOUNDRIES US Inc Milpitas CA 95035 USA

ISBN: (纸本)9780819489838

This paper addresses the framework for building critical recommended rules and a methodology for devising scoring models using simulation or silicon data. Recommended rules need to be applied to critical layout configurations (edge or polygon based geometric relations), which can cause yield issues depending on layout context and process variability. Determining of critical recommended rules is the first step for this framework. Based on process specifications and design rule calculations, recommended rules are characterized by evaluating the manufacturability response to improvements in a layout-dependent parameter. This study is applied to critical 20nm recommended rules. In order to enable the scoring of layouts, this paper also discusses a CAD framework involved in supporting use-models for improving the DFM-compliance of a physical design.

关键词： DFM scoring yield modeling CAD Monte-Carlo based process simulation DRC LFD printability simulation using OPC models MAS recommended rules sub-20nm technology and physical design verification

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design and manufacturability Tradeoffs in Unidirectional & Bidirectional Standard Cell Layouts in 14 nm node

Design and Manufacturability Tradeoffs in Unidirectional & B...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Vaidyanathan, Kaushik Ng, Siew Hoon Morris, Daniel Lafferty, Neal Liebmann, Lars Bender, Mitchell Huang, Wenbin Lai, Kafai Pileggi, Larry Strojwas, Andrzej Carnegie Mellon Univ 5000 Forbes Ave Pittsburgh PA 15213 USA IBM Corp Hopewell Jct NY USA

ISBN: (纸本)9780819489838

The 14 nm node is seeing the dominant use of three-dimensional FinFET architectures, local interconnects, multiple patterning processes and restricted design rules. With the adoption of these new process technologies and design styles, it becomes necessary to rethink the standard cell library design methodologies that proved successful in the past. In this paper, we compare the design efficiency and manufacturability of standard cell libraries that use either unidirectional or bidirectional Metal 1. In contrast to previous nodes, a 14 nm 9-track unidirectional standard cell layout results in up to 20% lower energy-delay-area product as compared to the 9-track bidirectional standard cell layout. manufacturability assessment shows that the unidirectional standard cell layouts save one exposure on Metal 1, reduces process variability by 10% and layout construct count by 2-3X. As a result, the unidirectional standard cell layout could serve as a key enabler for affordable scaling.

关键词： Standard Cell Library design for manufacturability design Technology Co-Optimization 14 nm Grating based design Regular design methodologies Profitable Scaling

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