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检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration IV"

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Pattern matching for double patterning technology-compliant physical design flows

Pattern matching for double patterning technology-compliant ...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Wang, Lynn T. -N. Dai, Vito Capodieci, Luigi GLOBALFOUNDRIES Milpitas CA 95035 USA

ISBN: (纸本)9780819489838

A pattern-based methodology for guiding the generation of DPT-compliant layouts using a foundry-characterized library of "difficult to decompose" patterns with known corresponding solutions is presented. A pattern matching engine scans the drawn layout for patterns from the pattern library. If a match were found, one or more DPT-compliant solutions would be provided for guiding the layout modifications. This methodology is demonstrated on a sample 1.8 mm(2) layout migrated from a previous technology. A small library of 12 patterns is captured, which accounts for 59 out of the 194 DPT-compliance check violations examined. In addition, the methodology can be used to recommend specific changes to the original drawn design to improve manufacturability. This methodology is compatible with any physical design flows that use automated decomposition algorithms.

关键词： Pattern matching double patterning decomposition design flow design rule check DRC Plus automated decomposition algorithm DPT

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In-design Hierarchical DFM Closure for DFM-Clean IP

In-Design Hierarchical DFM Closure for DFM-Clean IP

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Tripathi, Vikas Subramanian, Jayathi Sharma, Puneet Chen, Kuang-Han Kasthuri, Bala Hurat, Philippe Layton, Larry Freescale Semicond Delhi India Freescale Semicond Austin TX USA Cadence Design Syst Inc San Jose CA 95134 USA Cadence Design Syst Inc Austin TX 78759 USA

ISBN: (纸本)9780819489838

This paper presents the requirements for the design for manufacturability (DFM) checks such as lithography, and Chemical and Mechanical Polishing (CMP) at 28nm technology node, and the need to perform these DFM checks, early in the design phase and with minimum overhead. As a result, this reduces the risk of uncovering some DFM issues at the design tape out time when the changes in a design become expensive. Because IP blocks can be targeted to multiple designs, it is a key requirement that the lithography and CMP checks are accurate and designer-friendly and are easily applied at block-level. This paper describes the block-based methodology that allows the IP designers to perform quickly a comprehensive DFM analysis, including lithography and long-range CMP effects. This paper also explains the integration of the DFM checks into the design flow and correlation results between the block and chip-level checks.

关键词： Chemical mechanical planarization design for manufacturing Computer aided design Lithography Metals Copper Curium Data modeling Neodymium System on a chip

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design-of-Experiments Based design Rule Optimization

Design-of-Experiments Based Design Rule Optimization

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Kagalwalla, Abde Ali Muddu, Swamy Capodieci, Luigi Zelnik, Coby Gupta, Puneet Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90024 USA GLOBALFOUNDRIES Inc Milpitas CA USA Sagantec Inc Santa Clara CA USA

ISBN: (纸本)9780819489838

design rules (DRs) are the primary abstraction between design and manufacturing. The optimization of DRs to achieve the correct tradeoff between scaling and yield is a key step in developing a new technology node. In this work we propose a design-of-experiments based framework to optimize DRs, where layouts are generated for different DR values using compaction. By analyzing the impact of DRs on layout scaling, we propose a novel Boolean minimization based approach to reduce the number of layouts that need to be generated through compaction. This methodology provides an automated approach to analyze several DRs simultaneously and discover area-critical DRs and DR interactions. We apply this methodology to middle-of-line (MOL) and Metal1 layer design rules for a commercial 20nm process. Our methodology results in 10 - 10(5) x reduction in the number of layouts that need to be generated through compaction, and demonstrates the impact of MOL and Metal1 DRs on the area of some standard cell layouts.

关键词： Statistical analysis Manufacturing Lithography Astatine design for manufacturability Double patterning technology Standards development Statistical modeling 193nm lithography

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design Level Variability Analysis and Parametric Yield Improvement Methodology

Design Level Variability Analysis and Parametric Yield Impro...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Maerz, Reinhard Keck, Martin Intel Mobile Commun D-85579 Neubiberg Germany

ISBN: (纸本)9780819489838

With the transition to the 32/28 nm platform parameter variations of device and circuit parameters are becoming increasingly important for performance, reliability and yield. Based on a sensitivity analysis, the paper compares the impact of lithography and CMP on circuit parameter variations. Coupling capacitances that can be described by geometrical parameters such as line width and thickness impact signal delay, crosstalk noise and power consumption. Variations of these capacitances thus contribute significantly to parametric yield loss. Based on field solver simulations the most critical devices and interconnections can be identified, providing valuable input during the chip design cycle.

关键词： design for Manufacturing (DfM) parametric yield improvement variability analysis

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Smart Double-Cut Via Insertion Flow With Dynamic design-Rules Compliance For Fast New Technology Adoption

Smart Double-Cut Via Insertion Flow With Dynamic Design-Rule...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Abdulghany, Ahmad Fathy, Rami Capodieci, Luigi Pathak, Piyush Madhavan, Sriram Malik, Shobhit Mentor Graphics Corp. (United States) GLOBALFOUNDRIES Inc. (United States)

ISBN: (纸本)9780819489838

As IC technologies shrink and via defects remain the same size, the probability of via defects increases. Redundant via insertion is an effective method to reduce yield loss related to via failures, but a large number of extremely complex design rules make efficient automatic via insertion difficult. This paper introduces an automatic redundant via insertion flow which is capable of adopting new technologies and complex design rules extremely quickly. Runtime and efficiency are optimized through a smart insertion scheduling technique. Our experiments show that it efficiently improves redundant via percentage, making designs more robust against via defects.

关键词： Yield Enhancement redundant via insertion physical verification

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Replacing design rules in the VLSI design cycle

Replacing design rules in the VLSI design cycle

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Hurley, Paul Kryszczuk, Krzysztof IBM Res Zurich Switzerland

ISBN: (纸本)9780819489838

We make a case for the migration of design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict ORC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the ORC Line Width error type ORC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

关键词： design Rule Check machine learning signal processing optical lithography

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A scoring methodology for quantitatively evaluating the quality of double patterning technology-compliant layouts

A scoring methodology for quantitatively evaluating the qual...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Wang, Lynn T-N. Madhavan, Sriram Malik, Shobhit Pathak, Piyush Capodieci, Luigi GLOBALFOUNDRIES Milpitas CA 95035 USA

ISBN: (纸本)9780819489838

A Double Patterning Technology (DPT)-aware scoring methodology that systematically quantifies the quality of DPT-compliant layout designs is described. The methodology evaluates layouts based on a set of DPT-specific metrics that characterizes layout-induced process variation. Specific metrics include: the spacing variability between two adjacent oppositely-colored features, the density differences between the two exposure masks, and the stitching area's sensitivity to mask misalignment. These metrics are abstracted to a scoring scale from 0 to 1 such that 1 is the optimum. This methodology provides guidance for opportunistic layout modifications so that DPT manufacturability-related issues are mitigated earlier in design. Results show that by using this methodology, a DPT-compliant layout improved from a composite score of 0.66 and 0.78 by merely changing the decomposition solution so that the density distribution between the two exposure masks is relatively equal.

关键词： double patterning technology LELE scoring yield design rules decomposition misalignment stitch density

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Advanced techniques for design assembly and characterization for the 14nm node with LFD using a Black Box API

Advanced techniques for design assembly and characterization...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Opitz, Juliann Torres, Andres Graur, Ioana Manhawy, Wael Kanodia, Suniti Shafee, Marwah Mohamed, Sarah Hassand, Ahmed Bickford, Jeanne Mentor Graph Corp 8005 SW Boeckman Rd Wilsonville OR 97070 USA IBM Corp Syst & Technol Grp Hopewell Jct NY 12533 USA Mentor Graph Corp Cairo Egypt IBM Corp Syst & Technol Grp Essex Jct VT 05452 USA

ISBN: (纸本)9780819489838

The need to quickly and flexibly characterize the design manufacturability increases as circuit design scales beyond the 22nm node. Improvements in design practices and design software are enabling this process. The use of carefully characterized design subunits (cells) in the general assembly of the chip is one way to ensure that products are optimized for these increasingly difficult lithographic process challenges. Additionally, software for assessing design robustness has been enhanced to deal with ever more complex resolution enhancement techniques. State of the art simulator and verification tool sets provide the necessary step of creating simulation contours and process variability bands upon which various checks can then be performed. The construction of these contours and bands is often hidden from the user as traditional single or double exposure processes of one or two masks are assumed to be used to create the final layout pattern. With the introduction of many different process techniques that include double or multiple patterning steps, such traditional assumptions are no longer valid. A new mechanism needs to be implemented that supports any type and combination of patterning processes in a simple yet accurate fashion to construct the process variability bands that will be used for verification of the pattern manufacturability of the layout. To address these concerns a new Black Box Interface (BBAPI) has been introduced that allows process teams to customize the generation of process variability objects to reflect the specific manufacturing steps of the Fab, without losing the data encapsulation needed to protect the process' intellectual property while maintaining the usability of litho friendly design (LFD) concepts during physical synthesis. The increased flexibility in creating contours and bands ultimately leads to more robust physical designs which are aware of every part of the patterning process. This paper describes the design and co-optimiza

关键词： Manufacturing Photomasks Optical lithography design for manufacturing Double patterning technology Lithography design for manufacturability Interfaces Resolution enhancement technologies Visualization

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Computational lithography work flows and design rule exploration automation

Computational lithography work flows and design rule explora...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Sethi, S. Stanton, William Lucas, Kevin Hiserote, Jay Hur, Duckhyung Choi, Rooli Synopsys Inc 1301 S Mopac ExpresswaySuite 201 Austin TX 78746 USA Synopsys Inc Hillsboro OR USA Samsung Electronics Hwasung South Korea

ISBN: (纸本)9780819489838

Lithography development has become extremely computationally intensive. For a particular technology node being developed, it is critical to determine the optimum source and OPC/RET for each layer. In this paper we present a flexible new computation system for automation of source, OPC and RET optimization of advanced lithography layers. Of course, before determining the optimum source/RET/OPC of any layer, it is equally critical to determine the design rules which can be manufactured at a particular technology node. The design rule computational lithography problem is a superset of the source/OPC/RET optimization problem. With an automated methodology, time for process development can be reduced dramatically if a process development engineer can determine the design rules through accurate, automated simulation of the entire flow.

关键词： Source mask optimization Optical proximity correction Optimization (mathematics) Computational lithography Atrial fibrillation Resolution enhancement technologies Lithography Computing systems Manufacturing process engineering

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Electrical design for manufacturability and Lithography and Stress Variability Hotspot Detection Flows at 28nm

Electrical Design for Manufacturability and Lithography and ...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Hurat, Philippe Zhu, Jianhao Teoh, Edward Cadence Design Syst Inc 2655 Seely Ave San Jose CA 95134 USA GLOBAL FOUNDRIES Singapore 738406 Singapore

ISBN: (纸本)9780819489838

Lithography and stress effects cause Layout Dependent Variability (LDV), which results in unexpected and unaccounted timing variations. Because standard cells yield unpredicted timing variation due to context differences, the LDV methodology includes the Cell Context Analysis (CCA) flow that provides designers a comprehensive framework to optimize the design layouts and tune the cell's electrical performance. Conventional static timing analysis tools do not incorporate the electrical impact due to nearby context proximity. The LDV methodology includes an Advanced Timing Analysis (ATA) flow that accounts for the electrical impact of cell contexts, which provides more accurate timing results and identifies new timing violations on critical paths. This paper presents the electrical DFM (eDFM) methodologies developed by GLOBALFOUNDRIES using Cadence (R) LEA (Litho Electrical Analyzer) at 28nm technology node. The paper also discusses about the CCA results for more than 40 contexts of each cell and reports mean delay variations of 3% or more.

关键词： Lithography Simulation of CCA and DLA aggregates Laser Doppler velocimetry design for manufacturability Silicon Transistors Standards development design for manufacturing Current controlled current source Instrument modeling

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