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检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration IV"

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Implications of triple patterning for 14nm node design and patterning

Implications of triple patterning for 14nm node design and p...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Lucas, Kevin Cork, Chris Yu, Bei Luk-Pat, Gerry Painter, Ben Pan, David Z. Synopsys Inc. (United States) Synopsys Inc. (France) Univ. of Texas (United States) The Univ. of Texas at Austin (United States)

ISBN: (纸本)9780819489838

The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.

关键词： lithographic design rules double patterning (DPT) triple patterning (TPT)

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A study of Pattern Variability for Device Performance

A study of Pattern Variability for Device Performance

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Kim, Tae-Heon Han, Dae-Han Hong, Ae-Ran Kim, Yong-Hyeon Lee, Joo-Sung Chu, Yun-Hye Lee, Kweon-Jae Park, Yong-Jik Samsung Elect Co Ltd Memory Div DRAM PA Team Hwasung City Gyeonggi Do South Korea

ISBN: (纸本)9780819489838

As semiconductor process technology scales down to sub 30nm process node and beyond dimensions, the printability and process window of the lithographic patterns are seriously reduced due to the fundamental limit of the lithography and process variations. In this paper, we introduce a various analysis methodology of pattern variability for higher device performance using with applications of DBV (design Based Verification). Pattern variability is affected by both pattern process margins and electrical margins such as distribution of gate length. Even if post lithography verification would carry out after model based OPC, Pattern variability is increased not only unpredictable OPC hotspots but also unanticipated hotspots by AEI loading skew in full-chip. Secondly, electrical hotspots which are extracted by tail distributions of gate length are not always reliable enough to represent critical path with gate length of full-chip. We constructed New OCV extraction flow with a full-chip pattern classification that is required for both gate distribution accuracy and analysis of gate tail patterns. In this report, we investigated about the relationship between a pattern feature and pattern distribution of transistor length.

关键词： design Based Verification OPC pattern variability hotspots post verification gate length

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Fully integrated litho aware PnR design solution

Fully integrated litho aware PnR design solution

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Beylier, Charlotte Moyroud, Clement Granger, Fabrice Bernard Robert, Frederic Yesilada, Emek Trouiller, Yorick Marin, Jean-Claude STMicroelectronics 850 Rue Jean Monnet F-38926 Crolles France Mentor Graph Dev Crolles F-38330 Montbonnot St Martin France

ISBN: (纸本)9780819489838

design For Manufacturing (DFM) is becoming essential to ensure good yield for deep sub micron technologies. As design rules cannot anticipate all manufacturing marginalities resulting from problematic 2D patterns, the latter has to be addressed at design level through DFM tools. To deploy DFM strategy on back end levels, STMicroelectronics has implemented a CAD solution for lithographic hotspots search and repair. This allows the detection and the correction, at the routing step, of hotspots derived from lithographic simulation after OPC treatment. The detection of hotspots is based on pattern matching and the repair uses local reroute ability already implemented in Place and Route (PnR) tools. This solution is packaged in a Fast LFD Kit for 28 nm technology and fully integrated in PnR platforms. It offers a solution for multi suppliers CAD vendors routed designs. To ensure a litho friendly repair, the flow integrates a step of local simulation of the rerouted zones. This paper explains the hotspots identification, their detection through pattern matching and repair in the PnR platform. Run time, efficiency rate, timing and RC parasitic impacts are also analyzed.

关键词： DFM pattern matching OPC Place and Route Hotspot repair

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Model-based searching method to find the integrated critical failure on the wafer

Model-based searching method to find the integrated critical...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Kang, Bong-Soo Chung, No-Young Park, Hyung-Kwan Lee, Suk-Joo Ku, Ja-Hum Samsung Elect Corp Youngin City 446711 Gyeonggi Do South Korea

ISBN: (纸本)9780819489838

Current metal integration process normally uses hard mask for dry etch process instead of resist to compensate thin resist thickness. As the pattern size becomes smaller, thinner resist thickness is required to get sufficient lithography process window. But this trend increases a risk of systematic hard defect like the metal line bridge in damascene process because of consumption in dielectric material during dry etch process. The sub-32nm patterning with the single exposure is almost on the edge with the 193nm immersion lithography. The smaller lithography CD makes the aerial image contrast worse, which means higher DC level in the unexposed area. This higher DC level, latent image, can sacrifice the resist thickness in the unexposed area and this recessed resist thickness is very harmful for the etch process with the current hard mask which may induce the metal line bridge. Although OPC verification step checks potential hot spot during mask type out flow, there is no predictable method to detect systematic potential defects described above. In this paper, we proposed a new method to detect such potential defects and discussed the performance with wafer result. With this predictable model based search method, the robust patterning process in the sub-32nm node can be developed.

关键词： Metal line bridge damascene process hard mask image contrast OPC verification

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design friendly double patterning

Design friendly double patterning

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Yesilada, Emek STMicroelectronics F-38926 Crolles France

ISBN: (纸本)9780819489838

Double patterning using 193nm immersion has been adapted as the solution to enable 2x nm technology nodes until the arrival of EUV tools. As a result the past few years have seen a huge effort in creating double patterning friendly design flows. These flows have so far proposed a combination of decomposition rules at cell level and/or at placement level as well as sophisticated decomposition tools with varying density, design iteration and decomposition complexity penalties. What is more, designers have to familiarize themselves with double patterning challenges and decomposition tools. In this paper an alternative approach is presented that allows the development of dense standard cells with minimal impact on design flow due to double patterning. A real case study is done on 20nm node first metal layer where standard cells are designed without considering decomposition restrictions. The resulting layout is carefully studied in order to establish decomposition or color rules that can map the layout into two masks required for double patterning but without the need of complex coloring algorithms. Since the rules are derived from a decomposition unaware design they do not in return impose heavy restrictions on the design at the cell or placement level and show substantial density gains compared to previously proposed methods. Other key advantages are a simplified design flow without complex decomposition tools that can generate a faster time to market solution all at the same time keeping designers isolated from the challenges of the double patterning. The derived design rules highlight process development path required for design driven manufacturing.

关键词： Logic 20 nm Double Patterning DPT Decomposition Metal1 coloring coloring conflicts design rules DRC

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TOUR GUIDE ROBOT: A PLATFORM FOR INTERDISCIPLINARY ENGINEERING SENIOR design PROJECTS

TOUR GUIDE ROBOT: A PLATFORM FOR INTERDISCIPLINARY ENGINEERI...

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ASEE Annual conference

作者： Yelamarthi, Kumar Cent Michigan Univ Elect Engn Mt Pleasant MI 48859 USA

ISBN: (纸本)9780878232413

Interdisciplinary projects involving electrical engineering (EE), mechanical engineering (ME), and computer science (CS) students are both exciting and difficult to conceptualize. Answering this challenge, this paper presents an interdisciplinary project platform based on tour guide robots. The combination of software, hardware, and mechanical design makes this platform an excellent choice for undergraduate student projects in both design and research aspects. This integration of complex programming, electrical hardware, and mechanical system design provides an excellent educational experience for undergraduate students. Also, this interdisciplinary platform is systematic and integrated that involves investigating a complex process or system with multiple design and research elements, such as wireless communication, control system design, statistical analysis, structural dynamics, and design for manufacturability. through working on this project, students will be able to study a complex engineering and technology system that: (1) exposes them to applied and cutting-edge technologies;(2) encourages them to participate in an integrated, interdisciplinary curriculum;and (3) involves them in methods of applied technology and skills necessary to transition from academic to professional environments.

关键词： Machine design

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Intra-Cell process Variability and Compact Modeling of LWR Effects: from Self-Aligned Multiple Patterning to Multiple-Gate MOSFETs

Intra-Cell Process Variability and Compact Modeling of LWR E...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Chen, Yijian Kang, Weiling Cheng, Qi Peking Univ Shenzhen Grad Sch Sch Comp & Informat Engn Shenzhen 518055 Guangdong Peoples R China

ISBN: (纸本)9780819489838

As promising paths to break the diffraction limit of optical lithography, several self-aligned multiple patterning (SAMP) techniques have been proposed to improve the resolution capability recently. In this paper, we show that SATP (self-aligned triple patterning) process variations differ significantly from conventional optical lithography process. It is found that mandrels fabricated by a SATP process usually come up with worse line-width roughness (LWR) and critical-dimension uniformity (CDU) than spacers do. In addition to that, the gap space between two neighboring spacers is often accompanied with a poor CDU. Similar to SATP process, the self-aligned quadruple patterning (SAQP) technique also brings its own characteristics of process variability along with the scaling capability. SAMP process variability (such as intra-cell variability and process multi-modality) and their impacts on device performance of the multiple-gate MOSFETs are discussed. Moreover, we develop an analytic double-gate MOSFET model to study the effects of LWR on both fin thickness and gate misalignment. Numerical simulations are carried out to verify the accuracy of our simplified model. This analytic approach provides an efficient method for compact modeling of LWR induced device variations.

关键词： Self-aligned multiple patterning (SAMP) self-aligned triple patterning (SATP) self-aligned quadruple patterning (SAQP) multiple-gate MOSFET FinFET line-width roughness (LWR)

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Analysis, Quantification, and Mitigation of Electrical Variability due to Layout Dependent Effects in SOC designs

Analysis, Quantification, and Mitigation of Electrical Varia...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： Wang, Yangang Zwolinski, Mark Appleby, Andrew Scoones, Mark Caldwell, Sonia Azam, Touqeer Hurat, Philippe Pitchford, Chris Univ Southampton Southampton Hants England Cambridge Silicon Radio Ltd Cambridge England Cadence Design Syst Inc San Jose CA 95134 USA Cadence Design Syst Bracknell RG12 OPH Berks England

ISBN: (纸本)9780819489838

Variability in performance and power of 40nm and 28nm CMOS cells is highly dependent on the context in which the cells are used. In this study, the effects of context on a number of clock tree cells from standard cell libraries have been investigated. The study also demonstrated how the Litho Electrical Analyzer (LEA) tool from Cadence (R) is used to analyze the context-dependent variability. During the study, it was observed that the device characteristics including V-th, I-dsat, and I-off are significantly affected by Layout Dependent Effects (LDE), resulting in variability of performance and power of standard cells. Moreover, the dummy diffusions acting as mitigation process offered limited improvement for the effects of context. On the other hand, the cell level variability due to stress was analyzed. So, it is suggested that the relative variability of a cell is determined by its size and structure, and the variability can be improved to some extent by editing the cells' structure. Based on the analysis of the physical sources and properties of LDE, this paper presents a set of layout guidelines for mitigating layout dependent variability of 40 and 28nm CMOS cells.

关键词： Transistors Diffusion Clocks Silicon Field effect transistors Molybdenum System on a chip CMOS technology Device simulation Instrument modeling

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Analysis of Layout-dependent Context Effects on Timing and Leakage in 28nm

Analysis of Layout-dependent Context Effects on Timing and L...

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SPIE conference on design for manufacturability through design-process integration VI ((DfM-DPI)/Joint conference of the Optical Lithography

作者： McGuinness, Patrick Sharma, Puneet Hurat, Philippe Fastada Austin TX 78704 USA Freescale Semicond Austin TX USA Cadence Design Syst Inc San Jose CA 95134 USA

ISBN: (纸本)9780819489838

In advanced process technologies, a layout context (that is the layout surrounding a cell) can impact the timing and leakage of a cell due to stress induced by the layout features, Well Proximity Effect (WPE), and other layout-dependent effects. The Litho Electrical Analyzer (LEA) tool from Cadence (R) is used to perform an analysis on 28nm standard cells in order to assess the variation in the timing and leakage characteristics due to the layout-dependent effects. During the study, the substantial leakage and timing shifts due to the layout contexts were observed. Moreover, the leakage variations were measured, and different levels of correlation of shifts across the PMOS transistors and the corresponding non-correlation between the PMOS and NMOS devices were also observed. Due to cancellation of the positive and negative variations in leakage, and because the leakage variation in Silicon is large, it is recommended to include a flat leakage margin without having added complexity to the leakage analysis flow. In addition, the timing was observed that impacts the slew and load conditions and identified conditions where shifts would be the greatest. Also, several mitigations were identified to reduce the variability of timing due to a context. This paper begins with describing the tools and methodologies used for the performance and power analysis of standard cells. It also explains the delay impact analysis, present delay simulation, Silicon-based results, and proposes guidelines to mitigate the un-modeled LDEs.

关键词： Transistors Silicon Data modeling Oscillators Chemical mechanical planarization Clocks Device simulation Standards development Etching Lithography

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design for manufacturability through design-process integration VI

Design for Manufacturability through Design-Process Integrat...

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2012 SPIE conference on design for manufacturability through design-process integration, DfM-DPI 2012

ISBN: (纸本)9780819489838

The proceedings contain 37 papers. The topics discussed include: layout optimization through robust pattern learning and prediction in SADP gridded designs;self-aligned double patterning (SADP) compliant design flow;design-of-experiments based design rule optimization;smart double-cut via insertion flow with dynamic design-rules compliance for fast new technology adoption;local loops for robust inter-layer routing at sub-20 nm nodes;analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs;design level variability analysis and parametric yield improvement methodology;analysis of layout-dependent context effects on timing and leakage in 28nm;variability aware compact model characterization for statistical circuit design optimization;design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14nm node;and a novel methodology for triple/multiple-patterning layout decomposition.

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