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检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration V"

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Pre-AI and post-AI design: Balancing human Creativity and AI Tools in the Industrial design process 24

Pre-AI and post-AI design: Balancing human Creativity and AI...

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2024 International conference on Artificial Intelligence and Future Education, AIFE 2024

作者： Tang, Xilin Windham, Jerrod Bush, Benjamin School of Industrial and Graphic Design Auburn University AuburnAL United States

ISBN: (纸本)9798400710650

The advancement of Artificial Intelligence (AI) is reshaping industrial design by enhancing creativity and productivity. This study explores the integration of AI tools-specifically ChatGPT, DALL·E, Midjourney, and vizcom-into the industrial design process and attempts to apply them in undergraduate industrial design education. By emphasizing the distinction between Pre-AI (divergent phase) and Post-AI (convergent phase) design stages, based on the design Council's Double Diamond model, the impact of AI-Assisted methods on creativity and the design process is examined. through two case studies involving a Golf Cart Project and a Conceptual Car Project, we analyze the balance between human creativity and AI technology to enhance innovation while maintaining the essential role of human judgment (design decision). The findings offer preliminary insights for transforming design education and practice, highlighting the importance of foundational design skills in the era of AI. © 2024 Copyright held by the owner/author(s).

关键词： design for manufacturability

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Automated IC design Flow Using Open-Source Tools and 180 nm PDK 67

Automated IC Design Flow Using Open-Source Tools and 180 nm ...

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67th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Jaramillo-Toral, Uriel Carlos Garcia-Lopez, Juan Ortega-Cisneros, S. Isaac Baungarten-Leon, Emilio Tones-Gonzalez, Cristian Sandoval-Ibarra, F. CINVESTAV GDL Zapopan Jalisco Mexico

ISBN: (纸本)9798350387186;9798350387179

This paper presents an academic project leveraging open-source tools, particularly OpenLane, in conjunction with the 180 nm process design Kit (PDK) provided by GlobalFoundries, for automating Integrated Circuit (IC) design, specifically digital design. This methodology significantly reduces the time and resources required to achieve high-quality functional ICs. The successful integration of GlobalFoundries' PDK ensures manufacturability. This work aims to inspire the digital design community to explore the potential of open-source tools and promote more accessible solutions in IC manufacturing. Two digital projects were designed, manufactured, and tested: a clock divider and a 7-segment display decoder. Experimental results show that the circuits operate at frequencies lower than 50MHz with a 3.3v bias.

关键词： Digital design design automation Open-source tools IC manufacturing

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IMvR: ENABLING IMMERSIvE design EXPLORATION AND process integration FOR ADDITIvE MANUFACTURING OF COMPLEX ORGANIC GEOMETRIES 19

IMVR: ENABLING IMMERSIVE DESIGN EXPLORATION AND PROCESS INTE...

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ASME 19th International Manufacturing Science and Engineering conference (MSEC) held jointly with the 52nd North American Research conference (NAMRC)

作者： Aryall, Manish Raj Deshpandel, Sourabh Aurisano, Jillian Anand, Sam Univ Cincinnati Ctr Global Design & Mfg Dept Mech & Mat Engn Cincinnati OH 45221 USA Univ Cincinnati Smart Mfg Lab Digital Futures Cincinnati OH 45206 USA Univ Cincinnati Dept Comp Sci DaVInCi Lab Cincinnati OH 45221 USA

ISBN: (纸本)9780791888100

Evaluating and representing intricate design, simulation, and process outcomes for organic geometries can present limitations on traditional computing devices (computers, phones, and tablets) and remains a formidable challenge. This deficit in recognizing critical manufacturability concerns may result in several design revisions and iterations. virtual Reality (vR) presents a compelling alternative to conventional 3D environments, particularly when visualizing and analyzing complex organic geometries during the part design and manufacturing stages. Our work focuses on developing an immersive virtual environment (ImvR) to evaluate and visualize design and process parameters for additive manufacturing of complex shapes. We create visualization-centric designs that empower users to render surface and volume-based part models for design exploration to identify and evaluate design for Additive Manufacturing (DfAM) features. These visualization-centric designs emphasize and enhance the detection of these DfAM features through corresponding visualized part models or through color plots shown to highlight these features. Further, we optimize the build using a genetic algorithm to formulate the best build orientation tailored to DfAM features. We create all the visualization-centric models for the different build orientations found optimally to showcase the impact of optimizing one DfAM feature on other corresponding parameters. On the process side, we implement a Digital Twin to visualize, control, and modify parameters in an FDM 3D printing process. The digital twin model mimics the real-time operation of the 3D printer, showing the generated print layer-by-layer. Bayesian Network, a predictive modeling algorithm, provides the recommended parameters for modifying the printing process. These modifications pertain to optimizing the ultimate tensile strength of the part model by varying bed temperature, speed, and layer height. Two case studies on complex geometries - a Topol

关键词： virtual Reality ChatGPT Digital Twin Immersive visualization process Optimization visualization Toolkit design for Additive Manufacturing (DfAM)

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design of a High Jitter Harmonic Injected Ring Oscillator for Entropy Sources

Design of a High Jitter Harmonic Injected Ring Oscillator fo...

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2024 IEEE International conference on Integrated Circuits, Technologies and Applications, ICTA 2024

作者： Ye, Ziyang Ikeda, Makoto University of Tokyo Tokyo Japan

ISBN: (纸本)9798331530709

in the field of modern cryptography and-information security, the generation of random numbers is crucial, with the quality of the entropy source being paramount. This study explores the design of Ring Oscillator (RO)-based entropy sources, noted for their high manufacturability and ease of integration. However, the jitter produced by naive ROs is insufficient for high-quality entropy. We propose a design that significantly enhances jitter performance through the introduction of a harmonic injection path. This approach maintains high synthesizability while incurring only modest increases in area and power consumption. Experimental results demonstrate that the modified RO,fa bricated using a 180 nm process, elevated the average min-entropy from 0.058 / bit to 0.351/bit, offering new insights and substantial support for the development of high-quality random number generators. © 2024 IEEE.

关键词： Random number generation

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Laser-Assisted Bonding of a Miniature Multichannel Laser Diode Chip to a Silicon Photonics Integrated Circuit with through-Silicon Alignment 10

Laser-Assisted Bonding of a Miniature Multichannel Laser Dio...

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10th IEEE Electronics System-integration Technology conference (ESTC)

作者： vlasov, Aleksandr A. Lehtinen, Santeri Lepukhov, Evgenii virtanen, Heikki Ojanen, Samu-Pekka viheriala, Jukka Guina, Mircea Tampere Univ ENS Fac Phys Unit Optoelect Res Ctr Tampere Finland

ISBN: (纸本)9798350390377;9798350390360

The progression of hybrid integration technology for compact electronics and photonics systems is placing increasing demands on the development of novel automated procedures capable of ensuring reliable integration with enhanced throughput. Concurrently, the complexity and density of components within packages, encompassing Micro-ElectroMechanical Systems (MEMS), wafer-level optics, photonics, and III-v optoelectronics, are on the rise. To tackle these challenges, a pioneering integration methodology based on laser-assisted bonding (LAB) is introduced. The devised LAB configuration employs an innovative bottom illumination/irradiation design coupled with simultaneous imaging through silicon, facilitating precise alignment for photonics waveguides. Additionally, the implementation of Automated Power Control in the LAB process safeguards against overheating of bonded surfaces, thereby enhancing integration process reliability and repeatability. through a practical demonstration, we validate the efficiency of the LAB technique by employing it for the integration of a multichannel 1x1 mm III/v chip onto a silicon photonic circuit. The localized application of heat during the LAB process rapidly elevates the temperature of the photonic circuit beyond the melting point of pre-deposited solder layers, resulting in successful bond formation with impedance levels in the hundredths of an Ohm range and shear bond force of 10.3 N/10.3MPa/1050.3gf, satisfying the MIL-STD-883H requirements (Methods 2019.8 and 2011.8F). Importantly, this process minimizes thermal-induced stress on bonded surfaces and mitigates warpage. This demonstration not only verifies the functionality of the LAB process but also underscores its potential to expand the frontiers of photonic integration. Particularly noteworthy is the rapid and energy-efficient nature of the LAB process, featuring bottom illumination/irradiation and simultaneous through-silicon imaging. Consequently, it facilitates bonding and

关键词： assembly processes laser-assisted bonding photonic integration silicon devices silicon photonics through-silicon vision infrared imaging infrared microscopy

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A process design Method for Multichip Module using Model Based Definition 23

A Process Design Method for Multichip Module using Model Bas...

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23rd International conference on Electronic Packaging Technology (ICEPT)

作者： Li, Yang Wu, Yilong Chen, Chunmei Zhang, Yanming Hou, Qifeng Zeng, Ce 29th Res Inst CETC Dept Microwave Integrat Ctr Chengdu Peoples R China

ISBN: (数字)9781665499057

ISBN: (纸本)9781665499057

Benefit from high performance, high integration density, high heat dissipation and relatively low cost, the application of MCM (multichip module) has spread from military, aerospace and mainframe computers to electronic system products such as automobiles, communications, industrial devices, instruments and medical equipment. However, unlike chip design or PCB design, there is no mature design method for MCM based on model. 2D drawing-based design software, such as AutoCAD, are still using for MCM design. Thus, the design file doesn't include sufficient manufacturing data for process design, such as manufacturability check and process flow design. In order to improve the actual efficiency and accuracy of the process design, a method based on model-based definition was approved. This method is applied in Allegro SiP Layout design platform and realized by secondary development using SKILL command language. through this method, a 3D model of MCM, which contains geometric dimension, cross-section of substrate, bill of materials (BOM), die type, bond wire and other definitive manufacturing data, is designed. With this model, an assembly manufacturability check, which evaluates the manufacturability and producibility of design model, can be applied along with designing. Then, a process flow design scheme, which includes the allocation of BOM, is generated using this design model. According to the test results of process design of MCM, this method was benefit for reducing design error, reducing reliance on manual experience, improving the automation of process design, and resulted in faster feedback loops, better decisions, and faster-to-market products.

关键词： process design Multichip module Model-based definition

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design Implementation of Synchronous FIFO-Synthesis, PNR, STA and Physical verification

Design Implementation of Synchronous FIFO-Synthesis, PNR, ST...

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2024 International conference on Smart Electronics and Communication Systems, ISENSE 2024

作者： Athira, J. Archa, P. Adersh, v. College of Engineering Trivandrum Micro and Nanoelectronics Department of ECE Kerala Trivandrum India

ISBN: (纸本)9798331528126

This paper presents a comprehensive methodology for the design and implementation of a Synchronous FIFO (First-In-First-Out) system, covering the entire ASIC (Application-Specific Integrated Circuit) flow from RTL (Register Transfer Level) to GDSII (Graphic Data System). The work details the critical phases involved in achieving synthesis, placement and routing (PnR), static timing analysis (STA), logic equivalence check (LEC), and physical verification, using industry-standard tools such as Cadence Genus, Synopsys ICC2, and Mentor Graphics Calibre. The design is synthesized using the Cadence Genus tool, followed by placement, clock tree synthesis (CTS), and routing with Synopsys ICC2. Static timing analysis is performed using Synopsys PrimeTime after parasitic extraction via StarRC, with necessary timing adjustments made through buffer insertion and gate sizing to meet performance specifications. Logic equivalence checks ensure functional correctness through both post-synthesis and post-route stages. Physical verification, including design rule checks (DRC) and antenna checks, is conducted using Cadence virtuoso and Mentor Graphics Calibre to ensure manufacturability. The Synchronous FIFO design, implemented on a 180nm process node, successfully meets timing and physical constraints, and the final GDSII file indicates the design's readiness for the next steps in the chip manufacturing process. The work emphasizes the importance of a rigorous and structured design flow to optimize performance, power, area, and timing, with potential for future work in low-power optimization and scalability. © 2024 IEEE.

关键词： Application specific integrated circuits

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Hand, Heart, and AI Harmony: Integrating Generative AI to Innovate Northern Thai Local Wisdom 28

Hand, Heart, and AI Harmony: Integrating Generative AI to In...

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28th International Computer Science and Engineering conference, ICSEC 2024

作者： Putjorn, Pruet Prapattong, Pollavat Boonleart, Omsin Hirunro, Cherdchart Charoensri, Chalongrat Champakaew, Wilawan Unroj, Pattayaporn Mae Fah Luang University Center of Excellence in AI and Emerging Technologies School of Information Technology Chiang Rai Thailand Mae Fah Luang University School of Liberal Arts Mekong Sub-Region Art and Culture Research Unit Chiang Rai Thailand Mae Fah Luang University School of Social Innovation Areabased Social Innovation Research Center Chiang Rai Thailand Mae Fah Luang University School of Social Innovation Chiang Rai Thailand Mae Fah Luang University School of Liberal Arts Chiang Rai Thailand Mae Fah Luang University Circular Economy for Waste-Free Thailand Research Center School of Science Chiang Rai Thailand

ISBN: (纸本)9798350366860

This paper investigates the application of Generative AI (GenAI) in the design processes of Thai Lue textiles, aiming to enhance creativity, sustainability, and cultural preservation. The study employs a three-phase methodology: Engagement and Ideation, AI integration and design Generation, and Human-AI Collaboration. In the first phase, community workshops with local students, designers, and artisans focused on capturing cultural values through hand-drawn designs inspired by community stories and personal reflections, emphasizing the 'Hand' and 'Heart' aspects to foster deep cultural connections and personal engagement. The second phase utilized AI tools like DALL-E to generate diverse design prototypes from detailed prompts, evaluating these AI-generated designs for cultural relevance and aesthetic appeal through qualitative interviews and observations. This phase demonstrated the "AI-Harmony"concept, illustrating AI's role in complementing human creativity and expanding design possibilities. The final phase featured collaborative workshops where artisans and designers refined the AI-generated designs, gathering feedback on AI tools' usability and creative impact. Card sorting techniques and Human-Computer Interaction (HCI) studies were used to refine and validate design components, highlighting the effective synergy between human creativity and AI. This phase accelerated the design process and ensured that the outputs were both innovative and culturally resonant. The study's findings reveal the potential of GenAI to blend traditional craftsmanship with modern design elements, enhancing creative efficiency and making traditional crafts more appealing to younger generations. Additionally, the Funnel of Human and GenAI Creation model demonstrated that integrating AI tools can significantly streamline the design process, reduce resource consumption, and promote sustainable production practices. This integration supports the preservation of cultural heritage while ada

关键词： design for manufacturability

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Systemverilog Based design of an Rv32I Compliant RISC-v processor Core 5

SystemVerilog Based Design of an RV32I Compliant RISC-V Proc...

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5th IEEE Global conference for Advancement in Technology, GCAT 2024

作者： Rajyan, Abhinav Saini, Gaurav Nit Kurukshetra School of Vlsi Design & Embedded Systems Haryana India

ISBN: (纸本)9798350376685

This paper presents the innovative design and implementation of an Rv32I-compliant RISC-v processor core using System verilog, aimed at advancing the understanding of RISC-v architecture through a modular and extensible approach. The design process involved the development and integration of critical components, including an Instruction Fetch module, Instruction Decode module, Register File, Arithmetic Logical Unit, Data Memory module, Control Unit, and Branch Control Unit, all seamlessly integrated into a top-level interface. Rigorous testing and verification procedures were conducted, demonstrating the processor core's capability to execute a comprehensive subset of the RISC-v instruction set with high reliability and efficiency. The modular design not only ensures robust functionality but also provides a scalable foundation for future enhancements, such as the incorporation of complex instructions and multi-cycle operations. The results affirm the processor's operational integrity and highlight its potential for further architectural innovations in RISC-v processor design. © 2024 IEEE.

关键词： Instruction Fetch ISA (Instruction Set Architecture) Register File RISC (Reduced Instruction Set Computer) Rv32I

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Systemverilog-SystemC TestBench Architecture for vLSI Chip design verification 32

SystemVerilog-SystemC TestBench Architecture for VLSI Chip D...

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32nd IFIP/IEEE International conference on very Large Scale integration, vLSI-SoC 2024

作者： Ismael, Mohammad Hroub, Ayman Naser, Nasib Orion Vlsi Technologies Rawabi Palestine Birzeit University Department of Electrical and Computer Engineering Ramallah Birzeit Palestine

ISBN: (纸本)9798331539672

Simulation-based verification of very-Large-Scale integration (vLSI) chip design is inevitable. However, the simulation speed can be a bottleneck in the verification process productivity. People tried to accelerate simulation-based verification through parallelization, emulation, and reducing the number of test scenarios, etc. In this paper, we exploited the power of abstraction of SystemC to design fast and accurate golden functional reference models. These reference models can be integrated in the Universal verification Methodology (UvM) based TestBench through Transaction Level Modeling (TLM). Thus, the UvM based TestBench interacts with the SystemC reference model to get the golden values, and use them for checking. We used the proposed methodology to verify the execution unit (EXU) of the open-source RISC-v based veeR EL2 processor core. The experimental results showed that the proposed TestBench architecture with SystemC reference model is up to 15x faster than the TestBench with Systemverilog reference model. © 2024 IEEE.

关键词： Integrated circuit design

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