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检索条件"任意字段=Conference on Design for Manufacturability through Design-Process Integration V"

共 766 条记录，以下是131-140 订阅

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The Packaging design of the 3.6kv Integrated SiC MOSFET Power Module

The Packaging Design of the 3.6kV Integrated SiC MOSFET Powe...

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International conference on Power Electronics and Motion Control (IPEMC)

作者： Jia Ning Wang Dong Lei Zhang Shao Lin Yu Shuang Zhao Nan Zhu Pinpin Chai Abel Luo Hefei University of Technology Hefei China Institute of Energy Hefei Comprehensive National Science Center Hefei China Zinsight Technology (Shanghai) Co. Ltd. Shanghai China

ISBN: (数字)9798350351330

ISBN: (纸本)9798350351347

SiC MOSFETs are gradually replacing Si-based devices due to their advantages in high temperature, high frequency, and high voltage applications. Applying SiC MOSFETs in medium to high-power scenarios, such as high-voltage inverters and solid-state transformers with around 10kv, can help reduce losses and decrease device volume, thereby increasing power density to a certain extent. However, the rated voltage and current of commercially available SiC MOSFETs are limited. To meet the demands of high-voltage, high-power applications, it is necessary to connect SiC MOSFETs in series and parallel. In this paper, a 3.6Kv/600A integrated power module was developed using 1200v/100A SiC MOSFET chips. The module consists of thirty-six SiC MOSFET chips connected in series and parallel. through optimized packaging design and the integration of dynamic and static equalizer devices and drive circuits within the module, voltage and current balance effects are achieved. The IPM module was assembled using a self-developed packaging platform. The results of the tests indicate that the module exhibits good voltage and current balancing effects.

关键词： MOSFET Silicon carbide Multichip modules process control High-voltage techniques voltage Transformers

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Low-noise high-dynamic-range single-photon avalanche diodes with integrated PQAR circuit in a standard 55 nm BCD 16

Low-noise high-dynamic-range single-photon avalanche diodes ...

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conference on Advanced Photon Counting Techniques XvI

作者： Keshavarzian, Pouyan Gramuglia, Francesco Kizilkan, Ekin Bruschini, Claudio Tan, Shyue Seng Tng, Michelle Chong, Daniel Quek, Elgin Lee, Myung-Jae Charbon, Edoardo Ecole Polytech Fed Lausanne EPFL Rue Maladiere 71b CH-2000 Neuchatel Switzerland GLOBALFOUNDRIES 60 Woodlands Ind Pk D St 2 Singapore Singapore Korea Inst Sci & Technol KIST Seoul 02792 South Korea

ISBN: (纸本)9781510650558;9781510650541

Single-photon avalanche diode (SPAD) based sensors and systems enable a variety of applications in biomedical, automotive, consumer, and security domains. While several established standard technologies, which can facilitate the design of SPAD-based systems are already in existence, challenges remain for the development of deep sub-micron monolithic integration of circuits and SPADs. In this work, we present SPADs along with pixel circuits in a standard GF 55 nm BCDL process. Two different designs demonstrate the flexibility allowed by the technology for a variety of applications. Both shallow and deep junction SPADs present excellent noise performance of less than 1 cps/mu m(2) at 3 v excess bias. An integrated passive-quench active-recharge (PQAR) circuit is used in conjunction with the SPADs, which enables a dead time of less than 2 ns, easily allowing for high dynamic range applications that require > 100 Mcps such as quantum communication and information technologies. The deep and shallow junction SPADs demonstrate an afterpulsing probability of < 0.5 % and < 2 % at 3v excess bias, respectively. The dead time is adjustable through analog control of the active-recharge circuit, allowing for afterpulsing reduction to below 0.1 % while maintaining Mcps operation. The shallow junction, which has a breakdown voltage of about 18 v and a peak sensitivity at 430 nm is particularly interesting for applications requiring low supply voltage, whereas the deep SPAD, which demonstrates > 4 % photon detection probability (PDP) at 940 nm, can be implemented in LiDAR sensors that require enhanced sensitivity at near-infrared (NIR) wavelengths. The measured timing jitter of both SPADs is < 50 ps FWHM at 3 v excess bias and 780 nm.

关键词： depth-sensing LiDAR photon counting pixel circuits single-photon avalanche diodes (SPADs) time-correlated single-photon counting (TCSPC)

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Harnessing ChatGPT for Model Transformation in Software Architecture: From UML State Diagrams to Rebeca Models for Formal verification

Harnessing ChatGPT for Model Transformation in Software Arch...

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IEEE International conference on Software Architecture Workshops (ICSAW)

作者： Zahra Moezkarimi Kevin Eriksson Albin Alm Johansson Alessio Bucaioni Marjan Sirjani School of Innovation Design and Engineering Mälardalen University Västerås Sweden

ISBN: (数字)9798331533366

ISBN: (纸本)9798331533373

Software architecture relies heavily on modeling techniques to describe, analyze, and verify system designs. The Unified Modeling Language (UML) is widely recognized as both a de facto and de jure standard for modeling various types of systems. While UML has formalized semantics that enhance consistency and precision, it is not inherently designed for model checking. Rebeca, an actor-based modeling language, is designed to enable formal verification of concurrent reactive systems. Previous efforts to bridge UML and Rebeca through model transformations have required combining multiple UML diagrams and a deep understanding of Rebeca, limiting practical applicability. In this paper, we explore the potential of leveraging large language models, specifically GPT-4, to automate the transformation of UML state diagrams into Rebeca models. Using a few-shot learning approach, we investigated the feasibility of this translation process. Initial results revealed that UML state diagrams alone were insufficient for generating accurate Rebeca models. To address this limitation, we augmented the diagrams with metadata, enabling GPT-4 to produce models that required only minor corrections to be executable in Rebeca's model-checking tool, Afra. Our findings demonstrate that LLMs hold promise in facilitating model transformations for software architecture, particularly for translating UML state diagrams into Rebeca models for formal verification. While not yet fully automated, this approach significantly reduces the effort required for transformation, paving the way for further research into the integration of LLMs into model-driven engineering practices.

关键词： Translation Software architecture Large language models Unified modeling language Semantics Model checking Model driven engineering System analysis and design Standards Formal verification

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design and Implementation of Smart Charter Web Application

Design and Implementation of Smart Charter Web Application

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International conference on Recent Trends in Advance Computing (ICRTAC)

作者： Dhamodharan Srinivasan Banupriya. N Hemalatha R vimalraj D Kirubhakaran A.v Shree Shivaani S Abishek. R. P. D Department of CCE Sri Eshwar College of Engineering Coimbatore India Department of Mathematics Sri Eshwar College of Engineering Coimbatore India

The Smart Charter Web Application is a modern solution for colleges to simplify and improve the process of booking venues. It was created using HTML, CSS, and JavaScript, and offers a simple and easy-to-use interface that ensures a smooth experience for faculty and staff. It integrates Enterprise Resource Planning (ERP) functionalities to optimize resource management, enabling efficient scheduling and utilization of college facilities. HTML structures the web pages, while CSS enriches the user experience with visually appealing styles and responsive design. JavaScript is pivotal in adding interactivity and dynamic functionality, fostering a seamless booking experience. Key features of the Smart Charter Web Application include user registration and authentication, an interactive venue availability calendar, booking management, and an admin panel. The application leverages ERP's capabilities to centralize data, improve coordination, and enhance decision-making processes. Integrating server-side technologies like *** and a database like MongoDB ensures secure user authentication, efficient data processing, and reliable storage. This robust backend support complements the front end, providing a seamless user experience. Overall, the Smart Charter Web Application revolutionizes the college venue booking process through its user-friendly interface, dynamic functionalities, and integration of ERP features.

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design of CMOS Readout Circuits for ISFET Aptasensor

Design of CMOS Readout Circuits for ISFET Aptasensor

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Ural Symposium on Biomedical Engineering, Radioelectronics and Information Technology (USBEREIT)

作者： Dmitriy Ryazantsev Andrey Sheshil vitaliy Grudtsov Elena Rybachek Amir Gabdrakhmanov Natalia Komarova Department of Integral Bio- and Nanosensors Scientific-Manufacturing Complex “Technological Centre” Zelenograd Russia

We present the design and integration of ISFET aptasensor readout circuits on a single silicon substrate, integrated into a 1.2-μm 5v complementary metal oxide semiconductor process. The ISFET is based on a MOSFET with its gate connected to a metal pad brought to the surface of the chip through passivation opening. The ISFET design was determined by the ratio of the areas of the MOSFET and the sensitive surface of the floating gate. An aluminum oxide film was formed as the sensitive surface. Readout circuits based on differential measurements have been developed to implement a differentiation circuit into the chip using an instrumentation amplifier and due to processing by an external device using a repeater circuit and a transimpedance amplifier. For all circuits, an amplifier with a calculated gain of more than 1000 and a phase margin of 60.4 degrees at a frequency of 5.77 MHz and a gain margin of 7 dB at a frequency of 10.3 MHz with a load of 15 pF and 50 kOhm was used. DC measurements of the manufactured circuits were carried out and their operability was shown in direct contact with a metal probe and in contact with a buffer solution biased using platinum reference electrode. For the repeater and instrumentation amplifier circuits, the linearity of the characteristics is close to 1, and for the transimpedance amplifier circuit more than 0.98. The developed device provides a basis for the development of aptasensors for biomarkers detection.

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Transdisciplinary Technology Mining of Advanced 6G Satellite Communication Innovations 29

Transdisciplinary Technology Mining of Advanced 6G Satellite...

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29th International-Society-of-Transdisciplinary-Engineering (ISTE) International conference on Transdisciplinary Engineering (TE)

作者： Trappey, A. J. C. Huang, Andy Z. C. Chen, Neil K. T. Pa, Regan J. S. Trappey, C. v. Li, K. A. Hung, L. P. Natl Tsing Hua Univ Dept Ind Engn & Engn Management Hsinchu Taiwan Natl Yang Ming Chiao Tung Univ Dept Management Sci Hsinchu Taiwan Natl Appl Res Labs Sci & Technol Policy Res & Informat Ctr Taipei 106 Taiwan

ISBN: (纸本)9781643683386;9781643683393

This research focuses on using natural language processing text mining approaches to make knowledge induction from the patent corpus within 6G satellite communication technologies. The domain ontology, that describes the transdisciplinary features of the knowledge taxonomy, is derived and organized in a hierarchical schema. The trends of innovation distributions within the ontology are further analyzed to discover the transdisciplinary R&D requirements. The technology mining process discovers that the advanced satellite infrastructure and its hardware/software integration are the enabler for seamless and high-speed communication network connectivity on land, sea, and sky. Seven main parts of "6G satellite communication" ontology schema and the taxonomy are text-mined from relevant patents and literature. 2357 domain patents (all with highly transdisciplinary nature) are collected and analyzed. During macro-analyses, trend of inventions, the leading assignees, and the distribution of technology categories are depicted. The micro-analyses discover the innovations of technological themes, technology function matrix showing R&D hot-spots and cold-spots, and the most critical sub-technologys' lifecycle maturities. The ultra-goal of this research is to discover the main trends and the potentials of satellite communication-related technologies through smart technology mining techniques, especially those requiring transdisciplinary R&D. Finally, the strategic research plan for technical-savvy countries (e.g., Taiwan focusing on semiconductor and IT design and manufacturing sectors) is presented, highlighting the necessary transdisciplinary R&D efforts for mobile telecommunication industry.

关键词： 6G satellite communication Non-terrestrial network NLP text mining Transdisciplinary R&D

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Consistent and Repeatable Testing of mMIMO O-RU across labs: A Japan-Singapore Experience

Consistent and Repeatable Testing of mMIMO O-RU across labs:...

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IEEE conference on vehicular Technology (vTC)

作者： Thanh-Tam Nguyen Mao v. Ngo Binbin Chen Mitsuhiro Kuchitsu Serena Wai Seitaro Kawai Kenya Suzuki Eng Wei Koo Tony Quek Singapore University of Technology and Design Singapore Rakuten Mobile Keysight Technologies

ISBN: (数字)9798331517786

ISBN: (纸本)9798331517793

Open Radio Access Networks (RAN) aim to bring a paradigm shift to telecommunications industry, by enabling an open, intelligent, virtualized, and multi-vendor interoperable RAN ecosystem. At the center of this movement, O-RAN ALLIANCE defines the O-RAN architecture and standards, so that companies around the globe can use these specifications to create innovative and interoperable solutions. To accelerate the adoption of O-RAN products, rigorous testing of O-RAN Radio Unit (O-RU) and other O-RAN products plays a key role. O-RAN ALLIANCE has approved around 20 Open Testing and integration Centres (OTICs) globally. OTICs serve as vendor-neutral platforms for providing the testing and integration services, with the vision that an O-RAN product certified in any OTIC is accepted in other parts of the world. To demonstrate the viability of such a certified-once-and-use-everywhere approach, one theme in the O-RAN Global PlugFest Spring 2024 is to demonstrate consistent and repeatable testing for the open fronthaul interface across multiple labs. Towards this, Japan OTIC and Asia Pacific OTIC in Singapore have teamed up together with an O-RU vendor and Keysight Technology. Our international team successfully completed all test cases defined by O-RAN ALLIANCE for O-RU conformance testing. In this paper, we share our journey in achieving this outcome, focusing on the challenges we have overcome and the lessons we have learned through this process.

关键词： vehicular and wireless technologies Automation Asia Open RAN Life estimation Massive MIMO Springs Standards Interoperability Testing

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Hammer: a modular and reusable physical design flow tool: invited 22

Hammer: a modular and reusable physical design flow tool: in...

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Proceedings of the 59th ACM/IEEE design Automation conference

作者： Harrison Liew Daniel Grubb John Wright Colin Schmidt Nayiri Krzysztofowicz Adam Izraelevitz Edward Wang Krste Asanović Jonathan Bachrach Borivoje Nikolić University of California Amazon SiFive Massachusetts Institute of Technology JITX

ISBN: (纸本)9781450391429

process technology scaling and hardware architecture specialization have vastly increased the need for chip design space exploration, while optimizing for power, performance, and area. Hammer is an open-source, reusable physical design (PD) flow generator that reduces design effort and increases portability by enforcing a separation among design-, tool-, and process technology-specific concerns with a modular software architecture. In this work, we outline Hammer's structure and highlight recent extensions that support both physical chip designers and hardware architects evaluating the merit and feasibility of their proposed designs. This is accomplished through the integration of more tools and process technologies---some open-source---and the designer-driven development of flow step generators. An evaluation of chip designs in process technologies ranging from 130nm down to 12nm across a series of RISC-v-based chips shows how Hammer-generated flows are reusable and enable efficient optimization for diverse applications.

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A systematic for realizing agile principles in the process of mechatronic systems development through individual selection of suitable process models, methods and practices 31st

A systematic for realizing agile principles in the process o...

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31st CIRP design conference 2021, CIRP design 2021

作者： Heimicke, Jonas Ng, Gha-Leng Krüger, Madita Albers, Albert Karlsruhe Institute of Technology Kaiserstrasse 10 Karlsruhe76131 Germany

Agile elements support development processes of manufacturing companies by enabling increased customer integration and improved responsiveness to unforeseen changes in the development environment. However, existing agile approaches do not fully meet the additional demands that mechatronics systems development requires of these approaches, for example because of existing organizational structures not considered in the agile approaches. This results in challenges which can lead to considerable deficiencies in the product (e.g. with regard to safety requirements) or the approaches are rejected again. For this reason, this paper analyses a variety of agile and conventional methodologies, process models, frameworks, methods and practices regarding their suitability for the targeted integration of agility into the development processes of manufacturing companies considering different criteria and requirements. A broad literature research was carried out and the development modules (methodologies, process models, frameworks, methods and practices) identified were examined with regard to their suitability for support at both strategic and operational level. The modules were evaluated, among other things, at the strategic level with regard to their suitability for the realization of existing basic principles of agile development of mechatronic systems and at the operational level with regard to the optimization of existing agility-influencing factors. Based on this, a systematic was developed, which supports developers in the selection of agile and conventional development modules according to the objectives, relevant fields of action and specific factors influencing the agile capabilities of organizational units. The developed systematic enables a situation- and demand-based implementation of agility plus increased probability of a sustainable introduction of agility. © 2021 Elsevier B.v.. All rights reserved.

关键词： Product development

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Acceleration Feedback Controller processor design of a Kids Personal Transporter (kPT)

Acceleration Feedback Controller Processor Design of a Kids ...

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IEEE Annual Southern Power Electronics conference (SPEC)

作者： Ronal P. Chand Ravinesh Chand Mansour Assaf Parmesh R. Naicker Shailendra v. Narayan School of Mathematical & Computing Sciences Fiji National University Suva Fiji School of Information Technology Engineering Mathematics & Physics The University of the South Pacific Suva Fiji

In robotics, one of the major tasks in prototyping a robot after validating it through simulations is the design of its controller and implementing on processor using a hardware descriptive language such as field programmable gate arrays (FPGA) board, very-large scale integration (vLSI) chip, and application-specific integrated circuit (ASIC). This paper presents the development of the embedded application-specific instruction set processor(ASIP) design for acceleration feedback control laws of a nonholonomic autonomous kids personal transporter (kPT) robot, which contains two front driven wheels and a rear free-wheeling castor for balance with an omnidirectional obstacle sensor of limited detection range. The acceleration control laws are extracted from the total potentials, which is developed from the Lyapunov based Control Scheme (LbCS). The acceleration controllers were validated through simulations in Wolfram Mathematica software. The design could be implemented in hardware like vLSI chip, ASIC chip or an FPGA board for fast prototyping. Hence, this would provide a personal transporter for kids regardless of their physical and cognitive skills or abilities for safe navigation as the rider does not need to control the transporter.

关键词： process control Wheels very large scale integration Robot sensing systems Hardware Mathematical models Mobile robots

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