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检索条件"任意字段=Conference on Embedded Processors for Multimedia and Communications"

共 69 条记录，以下是1-10 订阅

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Proceeding of SPIE - embedded processors for multimedia and communications

Proceeding of SPIE - Embedded Processors for Multimedia and ...

引用

embedded processors for multimedia and communications

The proceedings contain 15 papers from the conference on SPIE - embedded processors for multimedia and communications. The papers discussed include: code compression for VLIW embedded processors;design and implementation of a fully programmable MPEG-2 transport demultiplexer for an STB application on DM642;programmable inner-product enhanced associative processor array;a low-power VLSI implementation for variable length decoder in MPEG-1 layer III;low-power high-performance 2D transform coprocessor for H.264 video compression standard and DSP platform-based JPEG2000 encoder with fast EBCOT algorithm.

关键词： embedded systems

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Reconfigurable embedded media processors

Reconfigurable embedded media processors

引用

IEEE International Performance, Computing, and communications conference

作者： Panchanathan, S Arizona State Univ Dept Comp Sci & Engn Collaborat Program Ubiquitous Comp CUbiC Tempe AZ 85233 USA

ISBN: (纸本)0780370015

The rapid proliferation of embedded multimedia applications necessitates efficient implementations which satisfy the computing demands of the various media processing algorithms. Several hardware and software solutions for media processing have appeared in the recent literature. The complexity, variety of techniques and tools associated with multimedia processing points to the opportunities for reconfigurable computing devices. These devices will be able to adapt the underlying hardware dynamically in response to changes in the input data or processing environment. In order to understand the static and dynamic nature of media processing techniques, there is a need to first perform a detailed complexity analysis on the set of candidate algorithms that encompass multimedia processing. This in turn will facilitate the design of a reconfigurable embedded hardware system. In this paper, we present a summary of the various implementation alternatives for media processing followed by the proposed approach for designing reconfigurable processors. We have chosen the latest multimedia standard namely, MPEG 4 as an example to demonstrate the potential for reconfigurability.

关键词： multimedia systems

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Energy-efficient H.264 video decoding on VLIW embedded processors

Energy-efficient H.264 video decoding on VLIW embedded proce...

引用

conference on embedded processors for multimedia and communications II

作者： Hu, Y Li, Q Kuo, CCJ Univ So Calif Integrated Media Syst Ctr Los Angeles CA USA

ISBN: (纸本)081945656X

The energy consumption profiling of the H.264 video decoder on VLIW embedded processors using the Trimaran simulator is conducted. Based on this study, we observe that the branch operations in the quarter-pixel (QP) interpolation and the DCT slow down the issue rate of the VLIW processors. Then, several new instruction architecture sets are proposed to address this issue. These new instructions can be used to speedup the issue rate, and reduce the total energy consumption. Finally, experimental results of the proposed instruction-level power-efficient strategies on the TI C6416 processor are reported and discussed.

关键词： VLIW embedded processor energy optimization H.264

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A reduced complexity frequency domain acquisition of DS-SS signals for embedded applications

A reduced complexity frequency domain acquisition of DS-SS s...

引用

conference on embedded processors for multimedia and communications II

作者： Akopian, D Sagiraju, PK Agaian, S Raju, GVS Univ Texas San Antonio San Antonio TX 78249 USA

ISBN: (纸本)081945656X

Most of the current wireless communication devices use embedded processors for performing different tasks such as physical layer signal processing and multimedia applications. embedded processors provide a reasonable trade-off between application specific implementation and hardware sharing by different algorithms for more optimal design and flexibility. At the same time the widespread popularity of these processors drives the development of algorithms specifically tailored for embedded environments. Fast Fourier Transform (FFT) is a universal tool, which has found many applications in communications and many application specific architectures and Digital Signal Processor (DSP) implementations are available for FFT [I]. In this paper our focus is in embedded algorithms for spread spectrum communication receivers, which are using FFT as an engine to compute convolutions. Using FFT-based correlators one can search over all possible so-called code phases of direct sequence spread spectrum (DS-SS) signal in parallel with fewer operations than conventional correlators do. However in many real-life scenarios the receiver is provided with a timing assistance which confines the uncertainty in code phase within a limited area. The FFT based search is becoming redundant and a reasonable strategy is to modify the FFT based methods for better utilization of embedded processor resources. In this paper we suggest a reduced complexity frequency domain convolution approach for the search over limited number of code phases.

关键词： Receivers Optical correlators Modulation Signal processing Global Positioning System Digital signal processing Convolution Satellites Demodulation Fourier transforms

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Compiler support for reducing the complexity of register file in media processors

Compiler support for reducing the complexity of register fil...

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conference on embedded processors for multimedia and communications

作者： Ju, XM Shi, C Yao, QD Zhejiang Univ Dept Informat Sci & Elect Engn Hangzhou 310027 Peoples R China

ISBN: (纸本)0819452122

Register file (RF) has been widely used in latest DSP and media processors. It is very important to include a reasonable RF configuration in the processor designs to help reducing the chip area, consumption and architecture complexity. DSP and media processors need many direct accesses to memory, and this will reduce register accessing. Another kind of reducing RF accessing frequency is bypassing or forwarding implemented by software mechanism, that the successive following instructions can directly use the result produced by the previous one through bypassing logic rather than RF. Therefore, the RF accessing frequency is decreased further. According to the experiment result, this new RF configuration not only satisfies the requirements of traditional media processors, but also is well applied to media processors with very long instruction word (VLIW) architecture.

关键词： Digital signal processing Logic Computer architecture Software Data storage Binary data Logic devices RF communications Cerium Information science

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Web surveillance system using platform-based design

Web surveillance system using platform-based design

引用

conference on embedded processors for multimedia and communications

作者： Lin, SY Tsai, TH Natl Cent Univ Dept Elect Engn Chungli 32054 Taiwan

ISBN: (纸本)0819452122

A revolutionary methodology of SOPC platform-based design environment for multimedia communications will be developed. We embed a softcore processor to perform the image compression in FPGA. Then, we plug-in an Ethernet daughter board in the SOPC development platform system. Afterward, a web surveillance platform system is presented. The web surveillance system consists of three parts: image capture, web server and JPEG compression. In this architecture, user can control the surveillance system by remote. By the IP address configures to Ethernet daughter board, the user can access the surveillance system via browser. When user access the surveillance system, the CMOS sensor presently capture the remote image. After that, it will feed the captured image with the embedded processor. The embedded processor immediately performs the JPEG compression. Afterward, the user receives the compressed data via Ethernet. To SUM LIP of the above mentioned, the all system will be implemented on APEX20K200E484-2X device.

关键词： multimedia communication platform-based design embedded processor

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Scalable transform accelerator for multimedia communications

Scalable transform accelerator for multimedia communications

引用

conference on embedded processors for multimedia and communications

作者： Akopian, D Takala, J Agaian, S Univ Texas San Antonio San Antonio TX 78249 USA

ISBN: (纸本)0819452122

Video compression is a, critical component, of many multimedia applications available today. The interest in multimedia has generated a lot of research in the area. of video coding in academy and industry alike and several successful standards have emerged, e.g., ITU-T H.261, H.263, ISO/IEC MPEG-1, MPEG-2 and MPEG-4. Transform video coding method is used by all video standards today. Discrete Cosine Transform (DCT) is the most popular transform for video coding and, in fact, is used in all current video-coding standards. We present scalable architectures for DCT transform to ad just the complexity to the considered application. The range of possible architectures includes sequential and parallel processing of transform butterflies at each stage.

关键词： scalable architecture DCT fast algorithms

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Code compression for VLIW embedded processors

Code compression for VLIW embedded processors

引用

conference on embedded processors for multimedia and communications

作者： Piccinelli, E Sannino, R STMicroelect Adv Syst Technol Agrate Brianza Italy

ISBN: (纸本)0819452122

The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

关键词： code compression embedded processors low power consumption VLIW

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MediaBench II Video: Expediting the next generation of video systems research

MediaBench II Video: Expediting the next generation of video...

引用

conference on embedded processors for multimedia and communications II

作者： Fritts, JE Steiling, FW Tucek, JA Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

ISBN: (纸本)081945656X

The first step towards the design of video processors and video systems is to achieve an accurate understanding of the major video applications, including not only the fundamentals of the many video compression standards, but also the workload characteristics of those applications. Introduced in 1997, the MediaBench benchmark suite provided the first set of full application-level benchmarks for studying video processing characteristics, and has consequently enabled significant research in computer architecture and compiler research for multimedia systems. To expedite the next Generation of systems research, the MediaBench Consortium is developing the MediaBench 11 benchmark suite, incorporating benchmarks from the latest multimedia technologies, and providing both a single composite benchmark suite as well as separate benchmark suites for each area of multimedia. In the area of video, MediaBench 11 Video includes both the popular mainstream video compression standards, such as Motion-JPEG, H.263, and MPEG-2, and the more recent next-generation standards, including MPEG-4, Motion-JPEG2000, and H.264. This paper introduces MediaBench 11 Video and provides a comprehensive workload evaluation of its major processing characteristics.

关键词： multimedia benchmarks workload evaluation media processors processor design MediaBench

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Low Power Schedule Algorithm for embedded multimedia Applications Basing on Imagine-L Processor

Low Power Schedule Algorithm for Embedded Multimedia Applica...

引用

14th IEEE International conference on High Performance Computing and communications (HPCC) / IEEE 9th International conference on embedded Software and Systems (ICESS)

作者： Cao, Shan Li, Zhaolin Chen, Zhixiang Jiang, Guoyue Wei, Shaojun Tsinghua Univ Tsinghua Natl Lab Informat Sci & Technol Inst Microelect Beijing 100084 Peoples R China Tsinghua Univ Tsinghua Natl Lab Informat Sci & Technol Res Inst Informat Technol Beijing 100084 Peoples R China Tsinghua Univ Dept Automat Beijing 100084 Peoples R China

ISBN: (纸本)9780769547497

The increasing high performance requirement of multimedia applications makes stream processors widely used for multimedia processing acceleration due to the powerful computation. Low power then becomes a critical challenge confronted by stream processors, especially in embedded and real-time situations. In this paper, a low power scheduling algorithm for embedded multimedia applications is proposed, and the H.264 encoding with intra-frame luma prediction is illustrated to demonstrate the schedule efficiency. As the fundamental of the scheduling algorithm, a multi-issued low power processor (Imagine-L) is first introduced which enables both DVFS, DPM techniques and multi-task parallelism. Then, a scheme which contains task mapping, V/F scaling and shutdown assignment is proposed for low power schedule. Task dependency, record dependency, task computation intensity and shutdown break-even point are all considered in the proposed algorithm to reduce power dissipation. For experimentation a power model is built for Imagine-L processor. The H.264 encoding application is implemented by the proposed algorithm, where 66% power consumption is reduced compared with the Imagine processor.

关键词： H.264 Schedule Low power Multi-issue DVFS DPM

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