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检索条件"任意字段=Conference on High Performance Algorithms and Software for Nonlinear Optimization"

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Distributed coordination in optimization algorithms

Distributed coordination in optimization algorithms

引用

high performance Computing and Networking Europe 1997 conference

作者： Di Martino, B Mazzeo, A Mazzocca, N Russo, S Univ Naples 2 Dipartimento Sci Informazione Naples Italy Univ Vienna Inst Software Technol & Parallel Syst A-1010 Vienna Austria Univ Naples Federico II Dipartimento Informat & Sistemist Naples Italy

ISBN: (纸本)3540628983

In this paper we present a parallel algorithm for the solution of discrete optimization problems, which is a typical example of highly irregularly structured problems. The Processor Farm model, well suited for this class of problems, has been modified to eliminate the presence of the coordinator, which represents a bottleneck for the parallel computation.

关键词： optimization

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Improving the performance of weighted Lagrange-multiplier methods for nonlinear constrained optimization

Improving the performance of weighted Lagrange-multiplier me...

引用

International conference on Tools for Artificial Intelligence (ICTAI)

作者： B.W. Wah Tao Wang Yi Shang Zhe Wu Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

nonlinear constrained optimization problems can be solved by a Lagrange-multiplier method in a continuous space or by its extended discrete version in a discrete space. These methods rely on gradient descents in the objective space to find high-quality solutions, and gradient ascents in the Lagrangian space to satisfy the constraints. The balance between descents and ascents depends on the relative weights between the objective and the constraints that indirectly control the convergence speed and solution quality of the method. To improve convergence speed without degrading solution quality, the authors propose an algorithm to dynamically control these relative weights. Starting from an initial weight, the algorithm automatically adjusts the weights based on the behaviour of the search progress. With this strategy, one is able to eliminate divergence, reduce oscillations, and speed up convergence. They show improved convergence behaviour of the proposed algorithm on both nonlinear continuous and discrete problems.

关键词： Lagrangian functions Constraint optimization Automatic control Convergence high performance computing USA Councils Uniform resource locators Degradation Heuristic algorithms Weight control

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Blind equalization of nonlinear communication channels using recurrent wavelet neural networks

Blind equalization of nonlinear communication channels using...

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International conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Shichun He Zhenya He Department of Radio Engineering South-East University Nanjing China

ISBN: (纸本)0818679190

This paper investigates the application of a recurrent wavelet neural network (RWNN) to the blind equalization of nonlinear communication channels. We propose a RWNN based structure and a novel training approach for blind equalization, and we evaluate its performance via computer simulations for a nonlinear communication channel model. It is shown that the RWNN blind equalizer performs much better than the linear CMA and the RRBF blind equalizers in the nonlinear channel case. The small size and high performance of the RWNN equalizer makes it suitable for high speed channel blind equalization.

关键词： Blind equalizers Communication channels Neural networks Recurrent neural networks Feedforward neural networks Helium Signal processing algorithms Electronic mail Application software Computer simulation

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DSP Quant: design, validation, and applications of DSP hard real-time benchmark

DSP Quant: design, validation, and applications of DSP hard ...

引用

International conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Chunho Lee D. Kirovski I. Hong M. Potkonjak Computer Science Department UCLA Los Angeles CA USA

Although the undeniable importance of high quality, efficient and effective DSP synthesis benchmark has been firmly and widely established, until now the emphasis of benchmarking has been restricted on assembling individual examples. In this paper we introduce the "ideal candidate benchmark methodology" which poses the development of the benchmark as well as defines a statistical and optimization problem. We first outline the goals and requirements relevant for the benchmark development. After discussing the computational complexity of the benchmark selection problem, we present a simulated annealing-based algorithm for solving this computationally intractable optimization task. Using this approach from 150 examples we select 12 examples for the new DSP Quant benchmark for DSP hard Real-Time applications. The DSP benchmark is statistically validated, and its application to the analysis and development of system-level synthesis algorithms is demonstrated,.

关键词： Digital signal processing Benchmark testing Application software Computer science Algorithm design and analysis Circuit testing Logic testing performance evaluation software performance software tools

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performance-power optimization of memory components for complex embedded systems

Performance-power optimization of memory components for comp...

引用

Annual Hawaii International conference on System Sciences (HICSS)

作者： C.H. Gebotys R.J. Gebotys Department of Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada

Optimizing performance and power during the design of embedded systems for real-time constrained applications is an important problem. This paper presents a network flow optimization technique to analyze power and performance tradeoffs for memory component design of an embedded system. The optimal number of external and internal memory accesses, memory sizes, and the number of extra computations (or data regeneration) for a number of tasks is determined. This is unlike previous research, which has only discussed ad hoc suggestions for this problem. The network flow approach can be solved to a globally optimal solution in polynomial time using very fast and efficient algorithms. Results for a large, complex, real industrial application-audio compression-show that this network flow technique provides up to 3.11 and 1.44 times improvement in power and performance respectively. This research is important for industry since power, performance and cost considerations at the early stages of design are crucial for mapping high-performance applications into cost-efficient and reliable systems.

关键词： Embedded system Costs Design optimization Communication industry Electronics industry Power system reliability Constraint optimization Real time systems Application software Polynomials

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optimization of custom MOS circuits by transistor sizing 96

Optimization of custom MOS circuits by transistor sizing

引用

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

作者： Andrew R. Conn Paula K. Coulman Ruud A. Haring Gregory L. Morrill Chandu Visweswariah IBM T. J. Watson Research Center and IBM Microelectronics Division Yorktown Heights NY Austin TX and Burlington VT

ISBN: (纸本)9780818675973

optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses LANCELOT, a large-scale nonlinear optimization package with an augmented Lagrangian formulation. Simple bounds are handled explicitly and trust region methods are applied to minimize a composite objective function. In the inner loop of the optimization, the fast circuit simulator SPECS is used to evaluate the circuit. SPECS is unique in its ability to efficiently provide time-domain sensitivities, thereby enabling gradient-based optimization. Both the adjoint and direct methods of sensitivity computation have been implemented in SPECS. To assist the user, interfaces in the Cadence and SLED design systems have been constructed. These interfaces automate the specification of the optimization task, the running of the optimizer and the back-annotation of the results on to the circuit schematic. JiffyTune has been used to tune over 100 circuits for a custom, high-performance microprocessor that makes use of dynamic logic circuits. Circuits with over 250 tunable transistors have been successfully optimized. Automatic circuit tuning has been found to facilitate design re-use. The designers' focus shifts from solving the optimization problem to specifying it correctly and completely. This paper describes the algorithms of JiffyTune, the environ

关键词： Circuits

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Development of a name translation system using CRAY T94

Development of a name translation system using CRAY T94

引用

International conference on high performance Computing in the Asia-Pacific Region

作者： Wentong Cai Peng Xu P. Wu H. Jyh School of Applied Science Nanyang Technological University Singapore Institute of Systems Science National University of Singapore Singapore

Natural language processing (NLP) is an important research direction, since it addresses the needs of the approaching information age. In this paper, we report our study on the problem of translating people's English names into their corresponding Chinese Pinyin names. A name translation system (NTS) has been developed based on statistical approaches. There are two components in the NTS: dictionary creation and name translation. The dictionary is generated using a statistics-based dictionary generator (SBDG), and the name translation is done by using a modified address normalization system (ANS). As in many other NLP applications, the SBDG and ANS suffer the drawback of requiring extremely large computational resources, both in terms of computation time and memory. To make the NTS fast and feasible, therefore, the use of a high-performance computer becomes necessary. The CRAY T94 is a powerful large-scale and general-purpose parallel-vector supercomputer. In this paper, we first describe the system design of the NTS, and then explain how the NTS is optimized to execute on the CRAY T94. The results we obtained are also discussed. Our experience shows that algorithms and data structures are very important in obtaining optimal performance. The performance monitoring/analysis tools provided by The CRAY T94 programming environment are also proved to be very useful in making optimization decisions. In addition, our study also demonstrates that using the CRAY T94, performance improvements can be achieved not only in the traditional areas of scientific computation but also in NLP applications.

关键词： Dictionaries Natural language processing Application software Large-scale systems Supercomputers System analysis and design Design optimization Data structures Monitoring performance analysis

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high performance software-only H.261 video compression on PC

High performance software-only H.261 video compression on PC

引用

Digital Video Compression - algorithms and Technologies 1996 conference

作者： Kasperovich, L INST INFORMAT TECHNOL SINGAPORE 0511SINGAPORE

ISBN: (纸本)0819420425

This paper describes an implementation of a software H.261 codec for PC, that takes an advantage of the fast computational algorithms for DCT-based video compression, which have been presented by the author at the February's 1995 SPIE/IS&T meeting. The motivation for developing the H.261 prototype system is to demonstrate a feasibility of real time software- only videoconferencing solution to operate across a wide range of network bandwidth, frame rate, and resolution of the input video. As the bandwidths of current network technology will be increased, the higher frame rate and resolution of video to be transmitted is allowed, that requires, in turn, a software codec to be able to compress pictures of CIF (352 X 288) resolution at up to 30 frame/sec. Running on Pentium 133 MHz PC the codec presented is capable to compress video in CIF format at 21 - 23 frame/sec. This result is comparable to the known hardware-based H.261 solutions, but it doesn't require any specific hardware. The methods to achieve high performance, the program optimization technique for Pentium microprocessor along with the performance profile, showing the actual contribution of the different encoding/decoding stages to the overall computational process, are presented.

关键词： video compression real-time processing software-only solution H.261

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System identification and machine setup of color xerographic machines using multivariate modeling and multiobjective optimization

System identification and machine setup of color xerographic...

引用

IEEE International conference on Control Applications

作者： Rai, S Xerox Corp Webster NY 14580 USA

ISBN: (纸本)078034104X

This paper describes an approach for performing system identification of the xerographic process and developing a model of the overall system. The experiment design is performed using orthogonal arrays. A nonlinear system model defining a vector mapping between the actuators and performance metrics is constructed using multivariate adaptive regression splines (MARS). These models provide a basis for providing automated and optimal machine setup on color machines. Multiobjective optimization techniques based on an underlying adaptive simulated annealing approach are discussed which are then used for determining the Pareto-optimal setpoints. The overall approach is applied to perform the automated setups of a high-end color machine, namely the Docucolor40. Experimental results show that high quality machine setups can be performed in an efficient and automated manner. The use of these setpoints as the basis of linearization about a nominal setpoint for use in linear control algorithms are also discussed.

关键词： xerography modeling optimization splines

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high speed video board as a case study for hardware-software co-design

High speed video board as a case study for hardware-software...

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Proceedings of the 1996 International conference on Computer Design, ICCD'96

作者： Herrmann, D. Maas, E. Trawny, M. Ernst, R. Rueffer, R. Seitz, M. Hasenzahl, S. Technische Universitaet Braunschweig Braunschweig Germany

We present experiences with the hardware/software co-design of a high-performance video board using co-synthesis and high-level synthesis tools. Consisting of a multiprocessor DSP, a coprocessor, 4 local memory banks and interface and switching circuits, the board executes one of two professional studio algorithms with very different characteristics. This board could replace a much larger system currently in use. While the CAD tools allowed for a widely automated what-if analysis and were also used for most of the final design, the design process also highlighted some missing links in an optimizing co-design of high performance systems. These missing links still prevent an efficient hardware/software optimization process. Flexibility requirements played an important role in the design process and had a massive impact on the target architecture, the hardware/software distribution, and the tool application.

关键词： Video signal processing

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