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检索条件"任意字段=Conference on High Performance Algorithms and Software for Nonlinear Optimization"
2069 条 记 录,以下是2051-2060 订阅
Quality-time tradeoffs in simulated annealing for VLSI placement
Quality-time tradeoffs in simulated annealing for VLSI place...
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IEEE Annual International Computer software and Applications conference (COMPSAC)
作者: S. Raman B. Wah Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA
A model is presented to characterize the relationship between the best solution (incumbent) found by an iterative algorithm (simulated annealing) and the time spent in achieving it. The target application has been cho... 详细信息
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27th ACM/IEEE Design Automation conference. Proceedings 1990
27th ACM/IEEE Design Automation Conference. Proceedings 1990
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27th ACM/IEEE Design Automation conference
The following topics are dealt with: HDL validation and intermediate format;probabilistic techniques in placement;binary decision diagrams;scheduling, mapping, and allocation techniques;timing-driven layout and verifi... 详细信息
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Computer-aided design of induction watthour meter
Computer-aided design of induction watthour meter
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IEEE Instrumentation and Measurement Technology conference
作者: Keren Ban China Instrument Society China
The author describes a newly established precise mathematical model and CAD (computer-aided design) algorithms for a high-overload induction watthour meter (the software package is called WATTCAD). The problem of comp... 详细信息
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TRANSISTOR SIZE optimization IN THE TAILOR LAYOUT SYSTEM  89
TRANSISTOR SIZE OPTIMIZATION IN THE TAILOR LAYOUT SYSTEM
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26TH DESIGN AUTOMATION CONF
作者: MARPLE, D Philips Research Laboratories Postbus 80000 5600 JA Eindhoven Netherlands
This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given a... 详细信息
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Fully automated layout generators for high-performance analog VLSI modules
Fully automated layout generators for high-performance analo...
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4th IEEE Region 10th International conference - TENCON '89
作者: Lee, Ji-Chien Gowda, Sudhir M. Sheu, Bing J. Dept of Electr Eng Univ of Southern California Los Angeles CA USA
algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layou... 详细信息
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IEEE International conference on Communications - ICC'89 IEEE International conference on Communications - ICC'89 IEEE International conference on Communications - ICC'89
IEEE International Conference on Communications - ICC'89 IEE...
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IEEE International conference on Communications - ICC'89
This conference proceedings contains 303 papers in this volume. The following topics are dealt with: operations support systems for ISDN;international standards for packet-switched service performance;asynchronous-tra... 详细信息
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TENCON '89: Fourth IEEE Region 10 International conference
TENCON '89: Fourth IEEE Region 10 International Conference
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4th IEEE Region 10th International conference - TENCON '89
This publication contains 249 conference papers. The following topics are dealt with: protocol and applications and packet switching;TDX-10 digital switching system technology;artificial intelligence and expert system... 详细信息
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Fully automated layout generators for high-performance analog VLSI modules
Fully automated layout generators for high-performance analo...
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IEEE Region 10 International conference TENCON
作者: J.-C. Lee S.M. Gowda B.J. Sheu Department of Electrical Engineering Signal and Image Processing Institute University of Southern California Los Angeles CA USA
algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layou... 详细信息
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Transistor Size optimization in the Tailor Layout System
Transistor Size Optimization in the Tailor Layout System
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Design Automation conference
作者: D. Marple Philips Research Laboratories Eindhoven Netherlands
This paper describes a combination transistor sizing/layout compaction tool used to synthesize high performance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given a... 详细信息
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BIPROCESSOR CONFIGURATION WITH ALTERNATING HIERARCHY FOR high SPEED PROCESS CONTROL.
Conference Proceedings - Annual Symposium on Computer Archit...
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conference Proceedings - Annual Symposium on Computer Architecture 1980年 443-449页
作者: Borangiu, Th. Dobrescu, R.
A biprocessor control configuration dedicated to high speed technological processes, such as electrical drives, is presented. In the proposed structure, a specialized asynchronous interface connects two INTEL 8085 mic... 详细信息
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