A model is presented to characterize the relationship between the best solution (incumbent) found by an iterative algorithm (simulated annealing) and the time spent in achieving it. The target application has been cho...
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A model is presented to characterize the relationship between the best solution (incumbent) found by an iterative algorithm (simulated annealing) and the time spent in achieving it. The target application has been chosen to be the placement of cells on a VLSI chip. The model is used to achieve a tradeoff between solution quality and time spent. This gives an idea of the time at which the iterative algorithm should be terminated when the marginal gain in solution quality is smaller than the marginal increase in cost (or time) spent. nonlinear regression analysis is used to predict the decrease in time with respect to improvement in solution quality. Experimental results on benchmark circuits are presented to show the errors of run-time prediction compared to a static prediction.< >
The following topics are dealt with: HDL validation and intermediate format;probabilistic techniques in placement;binary decision diagrams;scheduling, mapping, and allocation techniques;timing-driven layout and verifi...
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ISBN:
(纸本)081869650X
The following topics are dealt with: HDL validation and intermediate format;probabilistic techniques in placement;binary decision diagrams;scheduling, mapping, and allocation techniques;timing-driven layout and verification;data management and version control;data path optimizationalgorithms;floorplanning;formal methods in design verification;logic synthesis and testability;layout synthesis of MOS digital cells;software engineering in design automation;Boolean methods;timing and routing optimization;layout compactors;circuit simulation;scheduling algorithms for high-level synthesis;logic simulation acceleration;data path synthesis;behavioral synthesis;performance-constrained routing;functional models for testing;decomposition and partitioning in logic synthesis;combinational test generation;and channel-oriented multilayer routing. Abstracts of individual papers can be found under the relevant classification codes in this or other issues.
The author describes a newly established precise mathematical model and CAD (computer-aided design) algorithms for a high-overload induction watthour meter (the software package is called WATTCAD). The problem of comp...
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The author describes a newly established precise mathematical model and CAD (computer-aided design) algorithms for a high-overload induction watthour meter (the software package is called WATTCAD). The problem of computing the dynamic induced magnetic and electric systems of the watthour meter is solved in WATTCAD with three new nonlinear equivalent circuits. The Monte Carlo method for tolerance analysis and an optimization technique have been programmed and improved for meter design. The user interface to WATTCAD was simplified and the amount of data to be entered minimized. The improved linear interpolation and secant algorithms are programmed for solving nonlinear equations of complex matrices which are used to describe the inductive electromagnetic phenomenon. As an example, the use of WATTCAD to design a new model watthour meter DD285 is discussed.< >
This paper describes a combination transistor sizing/layout compaction tool used to synthesize highperformance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given a...
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ISBN:
(纸本)0897913108
This paper describes a combination transistor sizing/layout compaction tool used to synthesize highperformance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.
algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layou...
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algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.
This conference proceedings contains 303 papers in this volume. The following topics are dealt with: operations support systems for ISDN;international standards for packet-switched service performance;asynchronous-tra...
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This conference proceedings contains 303 papers in this volume. The following topics are dealt with: operations support systems for ISDN;international standards for packet-switched service performance;asynchronous-transfer-mode (ATM) switching, optical technologies for local distribution;cellular, portable, and personal communications;satellite communications using portable earth terminals;advances in echo-cancelling algorithms and implementation;communication over nonlinear/fading channels;telecommunication applications in health care, education, and rural service;operations standards;performance and operations issues for international voice services;high-speed packet network (ATM) performance;optical communications;advanced satellite communications technologies;advanced equalization and coding techniques for high-speed transmission over the digital subscriber loop network;efficient modulation techniques for spectrum management;communications for intelligent manufacturing systems;MAN architectures;optical processing, multiplexing and switching;advanced digital radio systems;digital signal processing;spread spectrum communications;multimedia network integration;analog fiber optic techniques;meteor burst communications;security and privacy in future communication networks;digital radio applications for the 1990s;software quality metrics;voice/image compression techniques;expert systems in communications;optical submarine cables;advanced satellite communications;signal processing for digital storage systems;and synchronization issues in communications.
This publication contains 249 conference papers. The following topics are dealt with: protocol and applications and packet switching;TDX-10 digital switching system technology;artificial intelligence and expert system...
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This publication contains 249 conference papers. The following topics are dealt with: protocol and applications and packet switching;TDX-10 digital switching system technology;artificial intelligence and expert systems;image processing;computer architecture;software for parallel processing;token passing LAN and applications;optimization and neural networks;digital modulation and modems;functional programming languages;architectures for parallel processing;application and implementation of Petri net concepts;signal processing and filters;array spectral analysis;advanced communication networks;TROPICO digital switching system;highperformance computing theory and applications;pattern recognition;fault tolerant computing;instrumentation and process control;data communication networks;speech analysis and recognition;computer hardware systems;robotics and automation;mobile radio;theoretical computer science and algorithms;distributed processing;LAN/WAN networking;applied expert systems;coding;C-DOT digital switching system;power delivery systems;rural communication;radar;parallel execution of functional programs;VLSI, ASICS and devices;transmission media and communication systems;office automation and databases;program transformation, synthesis and analysis;and power electronics.
algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layou...
详细信息
algorithms and a software implementation of a fully automated analog layout generation program are described. Device matching, area compaction, and parasitic/noise minimization are the key concerns in the analog layout generation. A new method to incorporate integrated-circuit reliability simulation results into the performance-driven optimization step is also presented. Experimental results on operational amplifiers, voltage comparators, and voltage-controlled oscillators show that the new generation program can produce high-quality circuit layouts efficiently.< >
This paper describes a combination transistor sizing/layout compaction tool used to synthesize highperformance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given a...
详细信息
This paper describes a combination transistor sizing/layout compaction tool used to synthesize highperformance CMOS circuits. This optimization tool is part of a large integrated layout system, called Tailor. Given any CMOS circuit layout, Tailor's transistor size optimizer will simultaneously adjust transistor sizes and compact the layout so that the minimum required area (cell pitch) for a specified upper bound on circuit delay is achieved. All delay paths are considered by modeling circuit delay with a logic independent delay graph. Tailor's optimizer globally optimizes circuit area (in one dimension) and delay by use of compaction and nonlinear programming algorithms. The optimizer does not yet optimize in two dimensions simultaneously or optimize hierarchical circuits. Results for a few optimized CMOS circuits are presented.
A biprocessor control configuration dedicated to high speed technological processes, such as electrical drives, is presented. In the proposed structure, a specialized asynchronous interface connects two INTEL 8085 mic...
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A biprocessor control configuration dedicated to high speed technological processes, such as electrical drives, is presented. In the proposed structure, a specialized asynchronous interface connects two INTEL 8085 microprocessors, the first of which performs the frequency control for two electric stepper motors, according to numerical two-axes interpolating algorithms, while the second works out the optimal controls (feedrate, speed) for a class of nonlinearperformance indexes, subject to nonlinear constraints of inequality type. Any one of the two microprocessors, logically placed on priority based hierarchical levels, can take hold of the master position in the control system and communicate over an eight bit data bus with the subordinate processing unit (slave). Real time processing diagrams are worked out, making therefore possible parallel high speed processing of both complex computing functions and of advanced optimizationalgorithms. Final remarks are made concerning some practical results for machine tools.
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