检索结果-内蒙古大学图书馆

4th International conference on Biomedical Signal and Image Processing

作者： Li, Chunbao Yang, Bo Univ Elect Sci & Technol China Sch Comp Sci & Engn Chengdu 611731 Peoples R China

ISBN: (纸本)9781450372244

Visual tracking is an active and challenging research topic in computer vision, as objects often undergo significant appearance variations caused by occlusion, deformation and background clutter. In recent years, many convolutional neural network based trackers have achieved impressive performance by integrating multi-layer features. However, in order to conduct multi-scale feature fusion, most of these trackers recover high-resolution presentations from low-resolution representations produced by a high-to-low resolution network, which tend to result in inaccurate feature maps or lose of details of the target object. In this paper, we propose an end-to-end region-based high-resolution fully convolutional Siamese network for tracking. In the tracker, we propose to extract the spatial information and semantic information of the target object using a high-resolution network that maintains rich high-resolution representations of the target object through the whole process. Furthermore, a set of position-sensitive score maps are obtained for all regions of the target template, and an adaptive weighting method is proposed to fuse score maps of multiple regions. Experimental results on the OTB50 and OTB100 benchmark datasets demonstrate that our tracker performs better than several state-of-the-art trackers while running in real-time.

关键词： Visual tracking Appearance variations high-resolution representation Siamese neural networks Position-sensitive score maps

来源：评论

学校读者我要写书评

暂无评论

SEBF: A single-chain based extension model of blockchain for fintech 29

SEBF: A single-chain based extension model of blockchain for...

引用

29th International Joint conference on Artificial Intelligence, IJCAI 2020

作者： Ji, Yimu Gu, Weiheng Chen, Fei Xiao, Xiaoying Sun, Jing Liu, Shangdong He, Jing Li, Yunyao Zhang, Kaixiang Mei, Fen Wu, Fei School of Computer Science Nanjing University of Posts and Telecommunications Nanjing China Jiangsu High Technology Research Key Laboratory for Wireless Sensor Networks Nanjing China Institue of High Performance Computing and Bigdata Nanjing University of Posts and Telecommunications Nanjing China Nanjing Center of HPC China Nanjing China Jiangsu HPC and Intelligent Processing Engineer Research Center Nanjing China Institute of Information Technology Nanjing University of Finance and Economics Nanjing China School of Software and Electrical Engineering Swinburne University of Technology Hawthorn Australia WeBank Co. Ltd. Shenzhen China College of Automation Nanjing University of Posts and Telecommunications Nanjing China

ISBN: (纸本)9780999241165

The traditional blockchain has the shortcoming that a single-chain can only deal with one or a few specific data types. The research question of how to make blockchain be able to deal with various data types has not been well studied. In this paper, we propose a single-chain based extension model of blockchain for fintech (SEBF). In the financial environment, we design a four-layer architecture for this model. By employing the external trusted oracle group and a financial regulator agency, a variety types of data can be effectively stored in the blockchain, such that the data type extension based on a single-chain is realized. The experimental results indicate that the proposed model can improve the efficiency of simplified payment verification. © 2020 Inst. Sci. inf., Univ. Defence in Belgrade. All rights reserved.

关键词： Blockchain

来源：评论

学校读者我要写书评

暂无评论

The implementation and optimization of parallel linpack on multi-core vector accelerator 21

The implementation and optimization of parallel linpack on m...

引用

21st IEEE International conference on high performance Computing and Communications, 17th IEEE International conference on Smart City and 5th IEEE International conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Liu, Zhong Tian, Xi Ma, Sheng College of Computer National University of Defense Technology Changsha410073 China

ISBN: (纸本)9781728120584

The Matrix2 Accelerator is a high performance multi-core vector processor for high-density computing. We design an efficient parallel implementation of the Linpack benchmark for the Matrix2. (1) We propose an efficient parallel matrix multiplication algorithm. It designs the optimal block parameters for the innermost sub-block matrix multiplication based on architecture characteristics of the Matrix2. It fully exploits multi-level parallelism including instruction-level parallelism, vector unit-level parallelism, and core-level parallelism;A vectorization method based on row computation for matrix multiplication is proposed, which avoids the inefficient column accesses and reduction summations between VPEs, and can obtain optimal kernel performance. (2) We propose an efficient parallel triangular matrix multiplication algorithm. It evenly distributes the irregular triangular matrix multiplication to different vector processing units, and fully leverage the computation capacity of the vector processor. It also supports in-place computation, which stores the result matrix into the space of the original multiplier matrix to save the memory consumption. (3) We propose an efficient parallel solving method of triangular equations. It significantly improves the computational efficiency by solving the equations in parallel using multiple cores. (4) We configure the L1D to a SRAM mode for finer software memory management. A data transfer strategy based on a two-level DMA double buffering scheme is proposed to optimize and smooth data transmission between different levels of the memory hierarchy. It allows the data movement to completely overlap with the kernel computation, allowing the kernel program to always run at peak speed. The experimental results on Matrix2 show that the efficiencies of double-precision parallel matrix multiplication, parallel triangular matrix multiplication, and Linpack computation are 96.08%, 91.47%, 84.58%, respectively. © 2019 IEEE.

关键词： Data transfer

来源：评论

学校读者我要写书评

暂无评论

An auto code generator for stencil on SW26010 21

An auto code generator for stencil on SW26010

引用

作者： Zhu, Xiaomin Zeng, Yunhui Wei, Yanjie Feng, Shengzhong Liu, Weiguo Balaji, Pavan Joint Engineering Research Center Health Big Data Intelligent Analysis Technology Center for High Performance Computing Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Shenzhen China Shandong Computer Science Center National SuperComputer Center in Jinan Jinan China Sclool of Software Shandong University Jinan China Argonne National Laboratory United States

ISBN: (纸本)9781728120584

Stencil is a basic building block widely used in many HPC areas and applications. It generally dominates the time cost and is critical to the overall performance. Given that heterogeneous many-core is frequently adopted to build super computers, porting and optimizing stencil codes on modern accelerator-based architectures is important. Porting is non-trivial, and optimization is more difficult as it requires better understanding of the underlying architecture. As a result, auto tuning targeting on accelerators such as GPU becomes a hot research topic. In this paper, we focus on tuning stencil automatically on SW26010, which is a heterogeneous many-core CPU equipped in Sunway TaihuLight Supercomputer, and mainly work on 2D stencil variants code in ROMS (Regional Ocean Modeling System). The code generator can generate codes running on slave cores for 50+ different FORTRAN stencil-alike loops in ROMS in seconds, and optimization methods are integrated into the generator as well. The performance is better than the directive based method (OpenACC) and the hand-drafted code by a junior programmer, and it is comparable compared with the code written by a senior programmer with several years of programming experience. © 2019 IEEE.

关键词： Supercomputers

来源：评论

学校读者我要写书评

暂无评论

MV-Sketch: A Fast and Compact Invertible Sketch for Heavy Flow Detection in Network Data Streams

MV-Sketch: A Fast and Compact Invertible Sketch for Heavy Fl...

引用

2019 IEEE conference on computer Communications, INFOCOM 2019

作者： Tang, Lu Huang, Qun Lee, Patrick P. C. Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong State Key Lab of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781728105154

Fast detection of heavy flows (e.g., heavy hitters and heavy changers) in massive network traffic is challenging due to the stringent requirements of fast packet processing and limited resource availability. Invertible sketches are summary data structures that can recover heavy flows with small memory footprints and bounded errors, yet existing invertible sketches incur high memory access overhead that leads to performance degradation. We present MV-Sketch, a fast and compact invertible sketch that supports heavy flow detection with small and static memory allocation. MV-Sketch tracks candidate heavy flows inside the sketch data structure via the idea of majority voting, such that it incurs small memory access overhead in both update and query operations, while achieving high detection accuracy. We present theoretical analysis on the memory usage, performance, and accuracy of MV-Sketch. Trace-driven evaluation shows that MV-Sketch achieves higher accuracy than existing invertible sketches, with up to 3.38 × throughput gain. We also show how to boost the performance of MV-Sketch with SIMD instructions. © 2019 IEEE.

关键词： Data structures

来源：评论

学校读者我要写书评

暂无评论

Latency-aware Hybrid Edge Cloud Framework for Mobile Augmented Reality Applications

Latency-aware Hybrid Edge Cloud Framework for Mobile Augment...

引用

IEEE Communications Society conference on Sensor and Ad Hoc Communications and Networks (SECON)

作者： Ayman Younis Brian Qiu Dario Pompili Department of Electrical and Computer Engineering Rutgers University New Brunswick NJ USA

ISBN: (数字)9781728166308

ISBN: (纸本)9781728166315

Mobile Augmented Reality (AR) has become a reality thanks to improvements in mobile hardware. Still, mobile AR lags behind its desktop counterpart in both latency and performance. Simple offloading to external computers has been attempted, but is not practical due to high communication latency and adverse user experience. In this paper, we propose a novel Mobile Edge Computing framework for Augmented Reality applications (MEC-AR). MEC-AR is designed to take advantage of 5G cellular networks and make optimized computation-offloading decisions in a multi-tiered hierarchy. A three-layered architecture involving the end user, the mobile edge, and finally the cloud is envisioned. In the context of MEC resource management, we cast a Mixed Integer Linear program (MILP) that aims at finding an efficient application placement on the MEC-AR layers to minimize the network latency. We evaluate the performance of our proposed MEC-AR framework by conducting extensive experimental analysis using images taken around Rutgers University. Simulation results coupled with real-time experiments on a small-scale MEC testbed show that our hierarchical computation mechanism improves the performance of mobile AR applications in terms of both energy consumption and network latency.

关键词： Servers Cloud computing Cameras Augmented reality Hardware Global Positioning System computer architecture

来源：评论

学校读者我要写书评

暂无评论

On the Design of high performance HW Accelerator through high-level Synthesis Scheduling Approximations

On the Design of High Performance HW Accelerator through Hig...

引用

Design, Automation and Test in Europe conference and Exhibition

作者： Siyuan Xu Benjamin Carrion Schafer Department of Electrical and Computer Engineering The University of Texas at Dallas TX USA

ISBN: (数字)9783981926347

ISBN: (纸本)9781728144689

high-level synthesis (HLS) takes as input a behavioral description (e.g. C/C++) and generates efficient hardware through three main steps: allocation, scheduling, and binding. The scheduling step, times the operations in the behavioral description by scheduling different portions of the code at unique clock steps (control steps). The code portions assigned to each clock step mainly depend on the target synthesis frequency and target technology. This work makes use of this to generate smaller and faster circuits by approximating the program portions scheduled in each clock step and by exploiting the slack between different scheduling step to further increase the performance/reduce the latency of the resultant circuit. In particular, each individual scheduling step is approximated given a maximum error boundary and a library of different approximation techniques. In order to further optimize the resultant circuit, different scheduling steps are merged based on the timing slack of different control step without violating the given timing constraint (target frequency). Experimental results from different domain-specific applications show that our method works well and is able to increase the throughput on average by 82% while at the same time reducing the area by 21% for a given maximum allowable error.

关键词： Clocks Delays Hardware Libraries Tools Processor scheduling

来源：评论

学校读者我要写书评

暂无评论

Practical Analysis on Running Speed for Efficient CNN Architecture Design 12

Practical Analysis on Running Speed for Efficient CNN Archit...

引用

12th International conference on Human System Interaction (HSI)

作者： Van-Thanh Hoang Jo, Kang-Hyun Univ Ulsan Sch Elect Engn Ulsan South Korea

ISBN: (纸本)9781728139807

Convolutional neural networks (CNNs) have shown significant performance in solving various artificial intelligence tasks in recent years. However, the increasing model size has raised challenges in adopting them in limited-resource applications. Recently, many research works try to build efficient networks which are as small as possible and have small computation time while still have acceptable performance. The state-ofthe-art architectures are ShuffleNetV2 and MobileNet. They use Depthwise Separable Convolution (DWConvolution) in place of standard Convolution to reduce the model size. Their designs are very efficient which follows many practical guild-lines. However, the ShuffleNetV2 has higher memory access cost (MAC) than the MobileNet. This paper evaluates these two networks on GPU and CPU with and without tuning step to show the advantages of each network. The experiments show that the MobileNet is faster on high-computational-optimization devices like GPU, whereas the ShuffleNetV2 is faster on low-computational-optimization devices like CPU when they have similar FLOPs.

关键词： CNN architecture practical computer vision

来源：评论

学校读者我要写书评

暂无评论

Recovery of Incomplete IoT Sensed Data using high-performance Extended-Input Neural-Like Structure 10

Recovery of Incomplete IoT Sensed Data using High-Performanc...

引用

10th International conference on Emerging Ubiquitous Systems and Pervasive Networks (EUSPN) / 9th International conference on Current and Future Trends of Information and Communication Technologies in Healthcare (ICTH)

作者： Izonin, Ivan Tkachenko, Roman Kryvinska, Natalia Zub, Khrystyna Mishchuk, Oleksandra Lisovych, Taras Lviv Polytech Natl Univ Dept Publishing Informat Technol S Bandera 12 UA-79013 Lvov Ukraine Univ Vienna Sch Business Econ & Stat Univ Ring 1 A-1010 Vienna Austria Comenius Univ Fac Management Odbojarov 10 Bratislava Slovakia Lviv Polytech Natl Univ Ctr Informat Support S Bandera 12 UA-79013 Lvov Ukraine Lviv Polytech Natl Univ Dept Management & Int Business S Bandera 12 UA-79013 Lvov Ukraine

The task of the recovery of incomplete IoT sensed data is considered. A high-performance extended-input neural network, which is constructed using a non-iterative neural -like structure and a Wiener polynomial for its solution, has been applied. Modelling of its work on the data collected by the IoT device was conducted. The research of hyperparameters selection of the proposed technique for missed data recovery was carried out. The number of neurons in the ANN's hidden layer and the polynomial degree for the effective method operation were selected by experimental way. It is established the significant reduction of the training time as well as the accuracy increase by reducing the ANN's hidden neurons number. A comparison of the proposed technique effectiveness with the state of-the -art has been carried out. The highest accuracy of its work is established in comparison with existing methods. The training time of the proposed technique was determined and compared with existing methods. (C) 2019 The Authors. Published by Elsevier B.V.

关键词： non-iterative training ANN extended-input SGTM Wiener polynomial incomplete datasets

来源：评论

学校读者我要写书评

暂无评论

Workshops of the seventh international brain-computer interface meeting: not getting lost in translation

引用

BRAIN-computer INTERFACES 2019年第3期6卷 71-101页

作者： Huggins, Jane E. Guger, Christoph Aarnoutse, Erik Allison, Brendan Anderson, Charles W. Bedrick, Steven Besio, Walter Chavarriaga, Ricardo Collinger, Jennifer L. Do, An H. Herff, Christian Hohmann, Matthias Kinsella, Michelle Lee, Kyuhwa Lotte, Fabien Mueller-Putz, Gernot Nijholt, Anton Pels, Elmar Peters, Betts Putze, Felix Rupp, Ruediger Schalk, Gerwin Scott, Stephanie Tangermann, Michael Tubig, Paul Zander, Thorsten Univ Michigan Dept Biomed Engn Neurosci Grad Program Dept Phys Med & Rehabil 325 East EisenhowerRoom 3017 Ann Arbor MI 48108 USA gtec Med Engn GmbH Guger Technol OG Schiedlberg Austria Univ Med Ctr Utrecht Dept Neurol & Neurosurg UMC Utrecht Brain Ctr Utrecht Netherlands Univ Calif San Diego Dept Cognit Sci La Jolla CA 92093 USA Colorado State Univ Dept Comp Sci Mol Cellular & Integrat Neurosience Program Ft Collins CO 80523 USA Oregon Hlth & Sci Univ Ctr Spoken Language Understanding Portland OR 97201 USA Univ Rhode Isl Dept Elect Comp & Biomed Engn Kingston RI 02881 USA Univ Rhode Isl Interdisciplinary Neurosci Program Kingston RI 02881 USA CREmed Corp Kingston RI USA Ecole Polytech Fed Lausanne Ctr Neuroprosthet Defitech Chair Brain Machine Interface CNBI Lausanne Switzerland Univ Pittsburgh Dept Phys Med & Rehabil Dept Vet Affairs VA Pittsburgh Healthcare Syst Pittsburgh PA USA Univ Calif Irvine Dept Neurol UC Irvine Brain Comp Interface Lab Irvine CA 92717 USA Maastricht Univ Sch Mental Hlth & Neurosci Maastricht Netherlands Max Planck Inst Intelligent Syst Dept Empir Inference Tubingen Germany Oregon Hlth & Sci Univ Inst Dev & Disabil Portland OR 97201 USA Swiss Fed Inst Technol Lausanne EPFL Defitech Fdn Chair Brain Machine Interface Lab Ctr Neuroprosthet Lausanne Switzerland Univ Bordeaux LaBRI CNRS Inria Bordeaux Sud OuestBordeaux INP Talence France Graz Univ Technol Graz Austria Univ Twente Fac EEMCS Enschede Netherlands Univ Bremen Cognit Syst Lab Bremen Germany Heidelberg Univ Hosp Spinal Cord Injury Ctr Heidelberg Germany SUNY Albany Natl Ctr Adapt Neurotechnol NYS Dept Hlth Wadsworth CtrAlbany Med CollDept Biomed Sci Albany NY 12222 USA Colorado State Univ Dept Media Commun Ft Collins CO 80523 USA Univ Freiburg Comp Sci Dept Brain State Decoding Lab Cluster Excellence BrainLinks BrainTools Breisgau Germany Univ Freiburg Comp Sci Dept Autonomous Intelligent Syst Lab Breisgau Germany Univ Washington Ctr Neuro

The Seventh International Brain-computer Interface (BCI) Meeting was held May 21-25th, 2018 at the Asilomar conference Grounds, Pacific Grove, California, United States. The interactive nature of this conference was embodied by 25 workshops covering topics in BCI (also called brain-machine interface) research. Workshops covered foundational topics such as hardware development and signal analysis algorithms, new and imaginative topics such as BCI for virtual reality and multi-brain BCIs, and translational topics such as clinical applications and ethical assumptions of BCI development. BCI research is expanding in the diversity of applications and populations for whom those applications are being developed. BCI applications are moving toward clinical readiness as researchers struggle with the practical considerations to make sure that BCI translational efforts will be successful. This paper summarizes each workshop, providing an overview of the topic of discussion, references for additional information, and identifying future issues for research and development that resulted from the interactions and discussion at the workshop.

关键词： Brain-computer interface brain-machine interface neuroprosthetics conference

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：