Community colleges play an important role in educating future engineers and scientists, especially students from traditionally underrepresented groups. Two-plus-two programs and articulation agreements between communi...
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Community colleges play an important role in educating future engineers and scientists, especially students from traditionally underrepresented groups. Two-plus-two programs and articulation agreements between community colleges and four-year institutions allow community college students to take their lower-division courses at local community colleges and then transfer to a university to complete their baccalaureate degrees. For many small community colleges, however, developing a comprehensive transfer engineering program can be challenging due to a lack of facilities, resources, and local expertise. As a result, many community college students transfer without completing the necessary courses for transfer, making timely completion of degrees difficult. Through a grant from the National Science Foundation, three community colleges in California collaborated to develop resources and teaching strategies to enable small community college engineering programs to support a comprehensive set of lower-division engineering courses that are delivered either completely online, or with limited face-to-face interactions. The biggest challenge in developing such strategies lies in designing and implementing courses that have lab components. This paper focuses on the development and testing of the teaching and learning resources for Engineering Graphics, which is a four-unit course covering the principles of engineering drawings, computer-aided design, and the engineering design process. The paper also presents the results of the implementation of the curriculum, as well as a comparison of the outcomes of the online course with those from a regular, face-to-face course. Student performance on labs and tests in the two parallel sections of the course are compared. Additionally student surveys conducted in both the online and face-to-face courses are used to document and compare students' perceptions of their learning experience, the effectiveness of the course resources, their us
The security of active distribution systems is critical to grid modernization along with deep renewable penetration, where the protection plays a vital role. Among various security issues in protection, conventional p...
The security of active distribution systems is critical to grid modernization along with deep renewable penetration, where the protection plays a vital role. Among various security issues in protection, conventional protection clears only 17.5% of staged high impedance faults (HIFs) due to the limited electrical data utilization. For resolving this problem, a detection and location scheme based on μ-PMUs is presented to enhance data processing capability for HIF detection through machine learning and big data analytics. To detect HIFs with reduced cost on data labeling, we choose expectation-maximization (EM) algorithm for semi-supervised learning (SSL) since it is capable of expressing complex relationships between the observed and target variables by fitting Gaussian models. As one of the generative models, EM algorithm is compared with two discriminative models to highlight its detection performance. To make HIF location robust to HIF impedance variation, we adopt a probabilistic model embedding parameter learning into the physical line modeling. The location accuracy is validated at multiple locations of a distribution line. Numerical results show that the proposed EM algorithm greatly saves labeling cost and outperforms other SSL methods. Hardware-in-the-loop simulation proves a superior HIF location accuracy and detection time to complement the HIF's probabilistic model. With outstanding performance, we develop software for our utility partner to integrate the proposed scheme.
With the rapid development of Internet of Things (IOT), IOT is more and more important. Also, it faces serious security issues. This paper analyzes Mirai's architecture. The core components are C & C server an...
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ISBN:
(纸本)9781538614822
With the rapid development of Internet of Things (IOT), IOT is more and more important. Also, it faces serious security issues. This paper analyzes Mirai's architecture. The core components are C & C server and Loader server that take charge of command and control, IOT equipments are in charge of broadcast and attack. Paper analyzes Botnet propagation model, Mirais infection attack procedure, impact factor and then proposes the corresponding anti-virus strategy.
Facial recognition is a rapidly developing application of machine learning. Face identification is specifically being adopted across security systems such as airports, perimeter security, and law-enforcement. In this ...
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This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple realtime computer vision pipelines. The presented tim...
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ISBN:
(数字)9781538685174
ISBN:
(纸本)9781538685174
This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple realtime computer vision pipelines. The presented time-sharing runtime framework manages an FPGA fabric that can be round-robin time-shared by different pipelines at the time scale of individual frames. In this new use-case, the challenge is to achieve useful performance despite high reconfiguration time. The paper describes the basic runtime support as well as four optimizations necessary to achieve realtime performance given the limitations of DPR on today's FPGAs. The paper provides a characterization of a working runtime framework prototype on a Xilinx ZC706 development board. The paper also reports the performance of streaming vision pipelines when time-shared. (1)
Major advancements in computational and sensor hardware have enormously facilitated the generation and collection of research data by scientists - the volume, velocity and variety of Big 'Research' Data has in...
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ISBN:
(数字)9781510618169
ISBN:
(纸本)9781510618169
Major advancements in computational and sensor hardware have enormously facilitated the generation and collection of research data by scientists - the volume, velocity and variety of Big 'Research' Data has increased across all disciplines. A visual analytics platform capable of handling extreme-scale data will enable scientists to visualize unwieldy data in an intuitive manner and guide the development of sophisticated and targeted analytics to obtain useable information. Reconfigurable Visual Computing Architecture is an attempt to provide scientists with the ability to analyze the extreme-scale data collected. Reconfigurable Visual Computing Architecture requires the research and development of new interdisciplinary technological tools that integrate data, real-time predictive analytics, visualization, and acceleration on heterogeneous computing platforms. Reconfigurable Visual Computing Architecture will provide scientists with a streamlined visual analytics tool.
Sparse triangular solver (SpTRSV) is an important and indispensable building block for many scientific applications. The parallelism of SpTRSV is exploited using Level-Set method in literature, however this method sti...
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ISBN:
(纸本)9781538666142
Sparse triangular solver (SpTRSV) is an important and indispensable building block for many scientific applications. The parallelism of SpTRSV is exploited using Level-Set method in literature, however this method still suffers from high synchronization cost and irregular global memory access especially on many-core architecture such as Sunway. In this paper, we propose an efficient implementation of SpTRSV using the massive computing resources on Sunway architecture. Specifically, we divide the 64 CPEs in a core group into three different roles, worker, router and storer. We also build a logical shared memory by carefully manipulating the scratchpad memory located in each storer and allow synchronization using the unique register communication on Sunway architecture. We partition the sparse matrix into multiple bands and replace the irregular global memory accesses with shared memory accesses, which significantly improves the data locality during the calculation of a band. Our experiments with 12 representative datasets demonstrate that our approach achieves up to 5.14x (2.65x on average) speedup.
With the rapid development of big data analytics frameworks, many existing highperformance computing (HPC) facilities are evolving new capabilities to support big data analytics workloads. However, due to the differe...
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ISBN:
(纸本)9783319699530;9783319699523
With the rapid development of big data analytics frameworks, many existing highperformance computing (HPC) facilities are evolving new capabilities to support big data analytics workloads. However, due to the different workload characteristics and optimization objectives of system architectures, migrating data-intensive applications to HPC systems that are geared for traditional compute-intensive applications presents a new challenge. In this paper, we address a critical question on how to accelerate complex application that contains both data-intensive and compute-intensive workloads on the Tianhe-2 system by deploying an in-memory file system as data access middleware;we characterize the impact of storage architecture on data-intensive MapReduce workloads when using Lustre as the underlying file system. Based on our characterization and findings of the performance behaviors, we propose shared map output shuffle strategy and file metadata cache layer to alleviate the impact of metadata bottleneck. The evaluation of these optimization techniques shows up to 17% performance benefit for data-intensive workloads.
Many complex problems, such as natural language processing or visual object detection, are solved using deep learning. However, efficient training of complex deep convolutional neural networks for large data sets is c...
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ISBN:
(数字)9781728144849
ISBN:
(纸本)9781728144856
Many complex problems, such as natural language processing or visual object detection, are solved using deep learning. However, efficient training of complex deep convolutional neural networks for large data sets is computationally demanding and requires parallel computing resources. In this paper, we present two parameterized performance models for estimation of execution time of training convolutional neural networks on the Intel many integrated core architecture. While for the first performance model we minimally use measurement techniques for parameter value estimation, in the second model we estimate more parameters based on measurements. We evaluate the prediction accuracy of performance models in the context of training three different convolutional neural network architectures on the Intel Xeon Phi. The achieved average performance prediction accuracy is about 15% for the first model and 11% for second model.
This paper presents the design and implementation of the new version of our software, the Parallel Runtime Environment for Multi-node Applications (PREMA 2.0). The motivation for the development of the runtime system ...
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