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检索条件"任意字段=Conference on High Performance Computer Modernization Program"

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EyeMath: Increasing Accessibility of Mathematics to Visually Impaired Readers

EyeMath: Increasing Accessibility of Mathematics to Visually...

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International computer Science and Engineering conference (ICSEC)

作者： Kanlayanee Dumkasem Padchaya Srisingchai Prapaporn Rattanatamrong Department of Computer Science Thammasat University Pathumthani Thailand

Mathematics education for visually impaired students is challenging because their learning materials are generally limited to braille books, and audiobooks. In order to increase the chance of learning mathematical content for people with visual impairment, this paper presents the design and development of a cloud-based mobile application called EyeMath, using serverless microservices in Amazon AWS. Users can provide images of page snippets for the application to process and read their content to the users. EyeMath segments an input image into smaller pieces and separates pieces that have only plain text from pieces with mathematical symbols. The mathematical-related pieces are further processed into an Abstract Syntax Tree (AST) and then parsed into Thai sentences. For plain text pieces, EyeMath relies on Tesseract OCR to convert them into text. Finally, results for all pieces are combined together systematically for the device's screen reader program to read aloud. The performance evaluation of the application shows high correctness in reading math content within test images and our usability testing confirms the potential usefulness of the application to visually impaired readers.

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Efficient Parallel Multi-bunch Beam-Beam Simulation in Particle Colliders

Efficient Parallel Multi-bunch Beam-Beam Simulation in Parti...

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International conference on high performance Computing

作者： Ioannis Sakiotis Kamesh Arumugam Desh Ranjan Balsa Terzic Mohammad Zubair Department of Computer Science Old Dominion University Norfolk Virginia NVIDIA Santa Clara California Old Dominion University Norfolk VA USA

Particle colliders are essential tools in the pursuit of understanding matter interactions in the universe. The tremendous cost of their operation and requirement for finetuning, make high-fidelity particle collider simulations essential in ensuring optimal operation. Simulations of the beam-beam effects of colliding particle bunches are extremely time-consuming since they include hundreds of billions of particles that collide millions of times per second. A high degree of parallelization is required to decrease the execution time of such simulations. GPUs present an opportunity towards making such simulations viable, though several challenges must be overcome in order to achieve efficient parallelization. One major challenge addressed in this paper is an efficient simulation of multiple bunch collision on a cluster of GPUs. The numerous colliding bunches are subject to scheduling constraints, which requires the utilization of an efficient collision schedule algorithm, all the while ensuring that the processors are not underutilized and communication overheads are low. We implemented two schemes on a 8-node cluster with four K40 GPUs on each node for a total of 32 GPUs. We demonstrated an almost linear speedup for large bunches with the number of GPUs.

关键词： program processors Particle beams Computational modeling Schedules Protons Colliding beam devices Clustering algorithms

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An In-Situ Visualization Approach for the K computer Using Mesa 3D and KVS

An In-Situ Visualization Approach for the K Computer Using M...

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International Supercomputing conference (ISC) on high performance

作者： Hayashi, Kengo Sakamoto, Naohisa Nonaka, Jorji Matsuda, Motohiko Shoji, Fumiyoshi Kobe Univ Kobe Hyogo Japan RIKEN Ctr Computat Sci Kobe Hyogo Japan

ISBN: (纸本)9783030024659;9783030024642

Although K computer has been operational for more than five years, it is still ranked in the top 10 of the Top500 list, and in active use, especially in Japan. One of the peculiarity of this system is the use of SPARC64fx CPU, with no instruction set compatibility with other traditional CPU architecture, and the use of a two-staged parallel file system, where the necessary data is moved from the user accessible GFS (Global File System) to a faster LFS (Local File System) for enabling high performance I/O during the simulation run. Since the users have no access to the data during the simulation run, the tightly coupled (co-processing) in-situ visualization approach seems to be the most suitable approach for this HPC system. For the visualization purposes, the hardware developer (Fujitsu) did not provide or support the traditional Mesa 3D graphics library on their SPARC64fx CPU, and in exchange, it provided a non-OSS (Open Source Software) and non-OpenGL visualization library with Particle-Based Volume Rendering (PBVR) implementation, including an API for in-situ visualization. In order to provide a more traditional in-situ visualization alternative for the K computer users, we focused on the Mesa 3D graphics library, and on an OpenGL-based KVS (Kyoto Visualization System) library. We expect that this approach can also be useful on other SPARC64fx HPC environments because of the binary compatibility.

关键词： Mesa3D graphics library SPARC64fx CPU KVS library Particle-Based Volume Rendering (PBVR) K computer

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A Novel Approach to Exponential Speedup of Simulation Events in Wireless Networks

A Novel Approach to Exponential Speedup of Simulation Events...

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International conference on Computing, Networking and Communications (ICNC)

作者： Ganti, Anand Onunkwo, Uzoma Van Leeuwen, Brian Scoggin, Michael P. Schroeppel, Richard Sandia Natl Labs Cyber Secur Initiat POB 5800 Albuquerque NM 87185 USA Sandia Natl Labs Trusted & Secure Syst POB 5800 Albuquerque NM 87185 USA Sandia Natl Labs Quantum Informat Sci POB 5800 Albuquerque NM 87185 USA

ISBN: (纸本)9781538636527

We demonstrate a new approach that yields exponential speedup of communication events in discrete event simulations (DES) of mobile wireless networks. With the trending explosive growth of wireless devices including Internet of things devices, it is important to have the capability to simulate wireless networks at large scale accurately. Unfortunately, current simulation techniques are inadequate for large-scale network simulation especially at high rate of total transmission events due to poor performance scaling. This has limited many studies to much smaller sizes than desired. We propose a method for attaining high fidelity DES of mobile wireless networks that leverages (i) path loss of transmissions and (ii) the relatively slower topology changes in a high transmission rate environment. Our approach averages a runtime of k(r)O(log N) per event, where N is the number of simulated wireless nodes, r is a factor of maximum transmission range, and k(r) is typically constant obeying k(r) << N.

关键词： Wireless networks Computational modeling Interference Runtime performance evaluation Communication system security

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Reliable Video Streaming over mmWave with Multi Connectivity and Network Coding

Reliable Video Streaming over mmWave with Multi Connectivity...

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International conference on Computing, Networking and Communications (ICNC)

作者： Drago, Matteo Azzino, Tommy Polese, Michele Stefanovic, Cedomir Zorzi, Michele Univ Padua Dept Informat Engn Padua Italy Aalborg Univ Dept Elect Syst Aalborg Denmark

ISBN: (纸本)9781538636527

The next generation of multimedia applications will require the telecommunication networks to support a higher bitrate than today, in order to deliver virtual reality and ultra-high quality video content to the users. Most of the video content will be accessed from mobile devices, prompting the provision of very high data rates by next generation (5G) cellular networks. A possible enabler in this regard is communication at mmWave frequencies, given the vast amount of available spectrum that can be allocated to mobile users;however, the harsh propagation environment at such high frequencies makes it hard to provide a reliable service. This paper presents a reliable video streaming architecture for mmWave networks, based on multi connectivity and network coding, and evaluates its performance using a novel combination of the ns-3 mmWave module, real video traces and the network coding library Kodo. The results show that it is indeed possible to reliably stream video over cellular mmWave links, while the combination of multi connectivity and network coding can support high video quality with low latency.

关键词： Streaming media Network coding Long Term Evolution Decoding Reliability Encoding Cellular networks

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ArchSampler: Architecture-Aware Memory Sampling Library for In-Memory Applications 36

ArchSampler: Architecture-Aware Memory Sampling Library for ...

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36th IEEE International conference on computer Design (ICCD)

作者： Zhou, Jian Wang, Jun Univ Cent Florida Dept Elect Engn & Comp Sci Orlando FL 32816 USA

ISBN: (纸本)9781538684771

With the explosive rate of data growth, the limited scalability of the DRAM technology defies the performance potentials for in-memory applications. Fortunately, emerging non-volatile memory (NVM) technologies, such as Phase-Change Memory (PCM) and Memristor, are promising candidates for replacing DRAM. Emerging NVMs are very dense, hence promise large capacities. Additionally, NVMs are non-volatile, thus enable persistent applications and byte-addressable files. Both density and persistency are key enablers for in-memory applications. On the other side, emerging NVMs are slower than DRAM, thus optimizing for locality and avoiding contentions are key aspects to unlock the NVM performance. In this paper, we study the impact of memory contentions and architecture-oblivious implementations on the performance of sampling based in-memory approximation. Sampling has become an imperative technique used to accelerate big data processing, especially in today's emerging in-memory computing. However, we observe multiple times slow-down for nave and default implementations of in-memory data sampling. Accordingly, we propose ArchSampler, an architecture-aware sampling library. The main idea is to exploits the free choice of data samples to dynamically select which bank as a host to serve memory requests. Hence, ArchSampler enables efficient and high performing sampling through employing its knowledge of the NVM architectural details to maximize data locality and avoiding inter thread contentions. Our evaluation shows that ArchSampler can achieve up to 1.62 speed up (1.20 on average) for different in memory applications.

关键词： Nonvolatile memory Instruction sets Random access memory Data analysis computer architecture Libraries Big Data applications

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Energy-Optimal Configurations for Single-Node HPC Applications

Energy-Optimal Configurations for Single-Node HPC Applicatio...

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International conference on high performance Computing & Simulation (HPCS)

作者： Vitor R. G. Silva Alex F. A. Furtunato Kyriakos Georgiou Carlos A. V. Sakuyama Kerstin Eder Samuel Xavier-de-Souza Dept. of Electronics and Microeletronics University of Mons Mons Belgium Directorate of Information Technology Instituto Federal do Rio Grande do Norte Natal Brazil Dept. of Computer Science University of Bristol Bristol United Kingdom Dept. of Computer Engineering and Automation Universidade Fedral do Rio Grande do Norte Natal Brazil

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

Energy efficiency is a growing concern for modern computing, especially for HPC due to operational costs and the environmental impact, considering that processors have an important role in this energy consumption. In this work, we propose a methodology to find energy-optimal frequency and number of active cores to run single-node HPC applications using an application-agnostic power model of the architecture and an architecture-aware performance model of the application. We characterize the application performance using machine learning, specifically the “Support Vector Regression” algorithm. Besides that, the power consumption is estimated by modeling CMOS dynamic and static power without knowledge of the application. So, The energy-optimal configuration is estimated by minimizing the product these two models outcomes, the power model and the performance model. Then, the final model can be used to find better frequency and number of cores to aim energy efficiency application execution. Results were obtained for four PARSEC applications and, with five different inputs shows that the proposed approach used substantially less energy when compared to the DVFS governor, in best cases and worst cases.

关键词： Semiconductor device modeling program processors Power demand Mathematical model Integrated circuit modeling Sockets Energy consumption

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Graph Partitioning for FEM Applications: Reducing the Communication Volume with DSHEM

Graph Partitioning for FEM Applications: Reducing the Commun...

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International conference on high performance Computing & Simulation (HPCS)

作者： José Luis González García Ramin Yahyapour Andrei Tchernykh Gesellschaft für wissenschaftliche Datenverarbeitung mbH Göttingen (GWDG) Göttingen Niedersachsen Germany Centro de Investigación Científica y de Educación Superior de Ensenada (CICESE) Ensenada Baja California Mexico

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

The finite element method is primarily utilized to numerically solve partial differential equations, most commonly by the use iterative methods, over a compact domain. The PDEs domain is represented by a mesh of information which needs to be distributed among all available processors in a parallel computer. Distributing the mesh, known as the mesh partitioning problem, is NP-complete. Much effort focuses on graph partitioning and parallelization to address it. We introduce a new vertex matching model called Directed Sorted Heavy Edge Matching intended to reduce the communication volume during FEM simulations and ensure efficient execution on distributed systems. Finally, we provide performance analysis of DSHEM and comment on its benefits.

关键词： program processors Finite element analysis Load management Load modeling Computational modeling Libraries Partitioning algorithms

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EnABLES: European infrastructure powering the internet of things 13

EnABLES: European infrastructure powering the internet of th...

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13th Smart Systems Integration conference, SSI 2019

作者： Hayes, Mike Donnelly, Julie Fagas, Giorgos Salot, Raphael Savelli, Guillaume Spies, Peter vom Boegel, Gerd Konijnenburg, Mario Breitung, Ben Gerbaldi, Claudio Romani, Aldo Gammaitoni, Luca Beeby, Steve Tyndall National Institute Cork Ireland CEA-Leti MINATEC Campus Grenoble France CEA-Liten MINATEC Campus Grenoble France Fraunhofer IIS Nürnberg Germany Fraunhofer IMS Duisburg Germany IMEC-NL Wireless System Solutions Eindhoven Netherlands KIT/HIU Institute for Nanotechnology Eggenstein-Leopoldshafen Germany GAME Lab Politecnico di Torino Italy Dept of Electrical Electronic and Info Engineering University of Bologna Italy NiPS Laboratory CEMIN University of Perugia Italy Electronics and Computer Science University of Southampton United Kingdom

ISBN: (纸本)9783800748785

The mission of EnABLES is to open up key research infrastructure in the Internet of Things (IoT) to all European researchers, from both academia and industry. Six research Institutes together with 5 knowledge hubs are providing access to researchers to enable them to create 'self-sustaining' energy solutions to 'power the internet of things' based on energy harvesting, storage, micro-power management and system integration activities. This paper provides an overview of the reasons why EnABLES is needed, particularly for enabling researchers address key challenges such as extending battery life of wireless IoT edge devices, and, where possible, eliminating the need for battery replacement. The ultimate goal of EnABLES is to create a 'starting community' to foster collaborations to address these challenges and opportunities & accelerate technology development. The 2 primary approaches used in EnABLES are outlined:(i) A transnational access (TA) and virtual access (VA) program open to all external stakeholders to do free-of-charge feasibility studies leveraging from the facilities and expertise of EnABLES partners. (ii) Joint Research Activities (JRAs) between partners. (Some examples of JRA activities are outlined at high level). Simulations and data libraries are retained in an open access repository with an emphasis on creating standardized and interoperable parts and understanding their system level behaviour. EnABLES also fosters internal collaboration between partners (JRAs) guided by needs and opportunities. A key goal of the project is to create standardised and interoperable libraries of parts & simulation tools for optimising system level performance. © VDE VERLAG GMBH

关键词： Internet of things

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Analysis and Characterization of GPU Benchmarks for Kernel Concurrency Efficiency 4th

Analysis and Characterization of GPU Benchmarks for Kernel C...

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4th Latin American conference on high performance Computing (CARLA)

作者： Carvalho, Pablo Drummond, Lucia M. A. Bentes, Cristiana Clua, Esteban Cataldo, Edson Marzulo, Leandro A. J. Univ Fed Fluminense Inst Computacao Niteroi RJ Brazil Univ Estado Rio De Janeiro Engn Sistemas & Computacao Rio De Janeiro Brazil Univ Fed Fluminense Programa Posgrad Engn Elet & Telecomunicoes Niteroi RJ Brazil Univ Estado Rio De Janeiro Ciencia Computacao Rio De Janeiro Brazil

ISBN: (纸本)9783319733531;9783319733524

Graphical Processing Units (GPUs) became an important platform to general purpose computing, thanks to their high performance and low cost when compared to CPUs. However, programming GPUs requires a different mindset and optimization techniques that take advantage of the peculiarities of the GPU architecture. Moreover, GPUs are rapidly changing, in the sense of including capabilities that can improve performance of general purpose applications, such as support for concurrent execution. Thus, benchmark suites developed to evaluate GPU performance and scalability should take those aspects into account and could be quite different from traditional CPU benchmarks. Nowadays, Rodinia, Parboil and SHOC are the main benchmark suites for evaluating GPUs. This work analyzes these benchmark suites in detail and categorizes their behavior in terms of computation type (integer or float), usage of memory hierarchy, efficiency and hardware occupancy. We also intend to evaluate similarities between the kernels of those suites. This characterization will be useful to disclosure the resource requirements of the kernels of these benchmarks that may affect further concurrent execution.

关键词： program processors

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