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International Joint conference on Neural Networks (IJCNN)

作者： Cai, Huayue Zhang, Xiang Luo, Zhigang Huang, Xuhui Natl Univ Def Technol Sci & Technol Parallel & Distributed Lab Changsha 410073 Hunan Peoples R China Natl Univ Def Technol Coll Comp Changsha 410073 Hunan Peoples R China Natl Univ Def Technol State Key Lab High Performance Comp Changsha 410073 Hunan Peoples R China Natl Univ Def Technol Coll Comp Dept Comp Sci & Technol Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9781509060146

Projective non-negative matrix factorization (PNMF) learns a non-negative projection matrix to project high-dimensional examples onto a lower-dimensional space spanned by the transpose of the learned projection matrix. Since PNMF can learn parts-based representation, it has attracted ample attention from computer vision community. However, existing PNMF methods either completely ignore labels of the dataset or endure the slow convergent optimization algorithm. In this paper, we propose a box-constrained discriminant PNMF (BDPNMF) method to address these issues. Specifically, BDPNMF jointly exploits the Fisher's criterion and the augmented Lagrangian multiplier (ALM) method into PNMF to boost discriminative capacity of the learned subspace and its efficiency. Experimental results on four popular face image datasets confirm the efficacy of BDPNMF compared to previous PNMF methods in quantity.

关键词： Optimization Linear programming Training Task analysis Convergence Face Testing

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Utilization of stellarium-based activity: its effectiveness to the academic performance of Grade 11 STEM strand students

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Journal of Physics: conference Series 2021年第1期1835卷

作者： Dharel P. Acut Rhett Anthony C. Latonio High School Department Sotero B. Cabahug FORUM for Literacy Consolacion Cebu 6001 Philippines Science Education Program Graduate School College of Teacher Education Cebu Normal University Osmeña Blvd. Cebu City Cebu 6000 Philippines

This study was carried out to understand and bring to fore if a simulation-based activity is effective on the academic performance of the students which has a general outlook to enhance meaningful science learning. This study focused on effectiveness of the stellarium-based activity on the academic performance of Grade 11 STEM Strand students of Sotero B. Cabahug FORUM for Literacy, School Year 2017 – 2018. The respondents of this study were composed of 28 students. The data pointed out that data analysis results shows that by conventional criteria, the differences of the scores on the different competencies is considered to be extremely statistically significant Results revealed that the stellarium-based activity is effective in teaching the cycles of the sky. Statistical results showed that the academic performance of the respondents improved when taught using the stellarium-based activity. Thus, it is best to learn astronomy using simulations. computer simulations have demonstrated the potential to facilitate this process by highlighting students' misconceptions and presenting plausible scientific conceptions. From the results, students are recommended to use stellarium, where the process often involves open-ended investigations into a question or a problem, requiring them to engage in evidence-based reasoning and creative problem-solving, as well as problem finding. Furthermore, science educators are encouraged to use stellarium in teaching the cycles of the sky and as anchors of the future teachers must always come equipped for these challenges charged on them, thus engaging students to learn and develop the potentials needed from them to take part for the betterment of today's world. Most importantly, future researchers are commended the development of a localized stellarium-based activity will greatly affect the academic performance of the student will surely boost their interest in learning astronomy education.

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A Transformation-Based Approach to Developing high-performance GPU programs 1

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11th International Andrei P. Ershov Informatics conference on Perspectives of System Informatics (PSI)

作者： Hagedorn, Bastian Steuwer, Michel Gorlatch, Sergei Univ Munster Munster Germany Univ Glasgow Glasgow Lanark Scotland

ISBN: (数字)9783319743134

ISBN: (纸本)9783319743134;9783319743127

We advocate the use of formal patterns and transformations for programming modern many-core processors like Graphics Processing Units (GPU), as an alternative to the currently used low-level, ad hoc programming approaches like CUDA or OpenCL. Our new contribution is introducing an intermediate level of low-level patterns in order to bridge the abstraction gap between popular high-level patterns (map, fold/reduce, zip, etc.) and imperative, executable code for many-cores. We define our low-level patterns based on the OpenCL programming model which is portable across parallel architectures of different vendors, and we introduce semantics-preserving rewrite rules that transform programs with high-level patterns into programs with low-level patterns, from which executable OpenCL programs are automatically generated. We show that program design decisions and optimizations, which are usually applied ad-hoc by experts, are systematically expressed in our approach as provably-correct transformations for high-and low-level patterns. We evaluate our approach by systematically deriving several differently optimized OpenCL implementations of parallel reduction that achieve performance competitive with OpenCL programs which are manually written and highly tuned by performance experts.

关键词： Parallel programming Rewrite rules Algorithmic patterns GPU OpenCL Code generation Skeletons Transformations

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The Library for Hadoop Deflate Compression Based on FPGA Accelerator with Load Balance

The Library for Hadoop Deflate Compression Based on FPGA Acc...

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IEEE International conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Haixin Du Jiankui Zhang Shihao Sha Cai Ye Qiuming Luo College of Computer Science and Software Engineering Shenzhen University NHPCC/Guangdong Key Laboratory of popular HPC and Guangdong Province Engineering Center of China-made High Performance Data Computing System Shenzhen China

ISBN: (数字)9781728126166

ISBN: (纸本)9781728126173

Hadoop application will produce lots of intermediate results in the map/reduce process that requires disk I/O and network transmission. By compressing the large-scale data of intermediate result, it will greatly improve disk access efficiently and reduce program run time. Hardware-accelerated solutions have become more desirable. This paper design a multi-FPGA compression accelerator on the Hadoop platform, and the system performance analysis compared with a software-only solution that mainly uses CPU to processing. The testing programs are zpipe, TestDFSIO and Terasort. In contrast with the software-only solution. The max speedup of zpipe is 6.55X (single FPGA) and 10.24X (dual FPGA), the max speedup of TestDFSIO is 6.28X (single FPGA) and 6.28X (dual FPGA), and the max speedup of Terasort application is up to 3.25X(single FPGA) and 3.35X(dual FPGA).

关键词： Handheld computers conferences computer science Software engineering Distributed databases Indexes

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A low cost method for determining the entire network path bandwidths of indirect high-performance computer networks 16

A low cost method for determining the entire network path ba...

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16th IEEE International Symposium on Parallel and Distributed Processing with Applications, 17th IEEE International conference on Ubiquitous Computing and Communications, 8th IEEE International conference on Big Data and Cloud Computing, 11th IEEE International conference on Social Computing and Networking and 8th IEEE International conference on Sustainable Computing and Communications, ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018

作者： Yan, Baicheng Zhou, Yi Xiao, Limin Yang, Zhang Wu, Hongyu Wei, Bing School of Computer Science and Engineering Beihang University Beijing100191 China Institute of Applied Physics and Computational Mathematics Beijing100094 China

ISBN: (纸本)9781728111414

Bandwidth is an important performance metric for high-performance computer network (HINET). How to determine large-scale HINET path bandwidths quickly and precisely is a highly pivotal challenge for parallel application performance analysis and prediction, optimizing end-to-end data transport performance, network management, etc. However, it is hard to determine the entire network point-to-point bandwidths of HINET since it often costs amounts of measurement time. Existing path bandwidth measurement methods focus on improving the accuracy of single path bandwidth measurement, however, lack considerations for reducing the entire network path bandwidths measurement times. To address this issue, we present an efficient method to generate the full-scale point-to-point bandwidth measurement plan for rapidly obtaining each path bandwidth in HINET. For evaluating, a source routing Fat-tree simulator and comprehensive experiments were conducted for different application scenarios. Both experimental and analysis showed that our method can reduce the measurement times significantly. In particular, compared to the exhaustive method, the measurement times of our method are one in 185 for the entire path bandwidth fault and can save 95% measurement times in 1024 nodes network with synthetic traffic. © 2018 IEEE.

关键词： Bandwidth

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A Cross-layer Adaptive Approach for performance and Power Optimization in STT-MRAM

A Cross-layer Adaptive Approach for Performance and Power Op...

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Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Sayed, Nour Bishnoi, Rajendra Oboril, Fabian Tahoori, Mehdi B. KIT Karlsruhe Germany

ISBN: (纸本)9783981926309

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate as a universal on-chip memory technology due to non-volatility. high density and scalability. However, high write energy and latency are major challenges in this memory technology due to the asymmetry and stochastic nature of the write operation. Typically, the write current is set for the minimum energy point, which can further impact the write latency. To mitigate these issues, we propose an adaptive write current scaling technique that adjusts the write current, and hence the write latency and energy based on the performance needs at run-time. Using this technique, optimal energy and performance points for write current are obtained using detailed device and system level analysis. Furthermore, we use run-time adaptation of write current by predicting the write access rate for the next execution phase. We evaluate the efficiency of the proposed approach on SPEC2000 applications for STT-MRAM-based L1 and L2-cache levels. The results show that the effective write latency of L1 and L2 is reduced by 52.4% and 55.7% with 7.6% and 1.4% area overheads, respectively, corresponding to the overall system performance optimization of 15.5% while the total memory energy consumption is increasing by only 3.2%.

关键词： Switches Random access memory computer architecture Magnetic tunneling Microprocessors performance evaluation Thermal stability

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A Demonstration of FPGA-based You Only Look Once version2 (YOLOv2) 28

A Demonstration of FPGA-based You Only Look Once version2 (Y...

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28th International conference on Field programmable Logic and Applications (FPL)

作者： Nakahara, Hiroki Shimoda, Masayuki Sato, Shimpei Tokyo Inst Technol Tokyo Japan

ISBN: (数字)9781538685174

ISBN: (纸本)9781538685174

We implement the YOLO (You only look once) object detector on an FPGA, which is faster and has higher accuracy. It is based on the convolutional deep neural network (CNN), and it is a dominant part of both the performance and the area. It is widely used in the embedded systems, such as robotics, autonomous driving, security, and drones, all of which require high-performance and low-power consumption. A frame object detection problem consists of two problems: one is a regression problem to spatially separated bounding boxes, the second is the associated classification of the objects within realtime frame rate. We used the binary (1 bit) precision CNN for feature extraction and the half-precision (16 bit) precision CNN for both classification and localization. We implement a pipelined based architecture for the mixed-precision YOLOv2 on the Xilinx Inc. zcul02 board, which has the Xilinx Inc. Zynq Ultrascale+ MPSoC. The implemented object detector archived 35.71 frames per second (FPS), which is faster than the standard video speed (29.9 FPS). Compared with a CPU and a GPU, an FPGA based accelerator was superior in power performance efficiency. Our method is suitable for the frame object detector for an embedded vision system.

关键词： Field programmable gate arrays computer architecture Graphics processing units Detectors Feature extraction Training Neural networks

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program Synthesis using Uniform Mutation by Addition and Deletion 18

Program Synthesis using Uniform Mutation by Addition and Del...

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Genetic and Evolutionary Computation conference (GECCO)

作者： Helmuth, Thomas McPhee, Nicholas Freitag Spector, Lee Hamilton Coll Clinton NY 13323 USA Univ Minnesota Morris MN 56267 USA Hampshire Coll Amherst MA 01002 USA

ISBN: (纸本)9781450356183

Most genetic programming systems use mutation and crossover operators to create child programs from selected parent programs. Typically, the mutation operator will replace a randomly chosen subprogram in the parent with a new, randomly generated subprogram. In systems with linear genomes, a uniform mutation operator can be used that has some probability of replacing any particular gene with a new, randomly chosen gene. In this paper, we present a new uniform mutation operator called Uniform Mutation by Addition and Deletion (UMAD), which first adds genes with some probability before or after every existing gene, and then deletes random genes from the resulting genome. In UMAD it is not necessary that the new genes replace old genes, as the additions and deletions can occur in different locations. We find that UMAD, with relatively high rates of addition and deletion, results in significant increases in problem-solving performance on a range of program synthesis benchmark problems. In our experiments, we compare this method to a variety of alternatives, showing that it equals or outperforms all of them. We explore this new mutation operator and other well-performing high-rate mutation schemes to determine what traits are crucial to improved performance.

关键词： mutation genetic operators Push program synthesis

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A Truthful FPTAS Mechanism for Emergency Demand Response in Colocation Data Centers

A Truthful FPTAS Mechanism for Emergency Demand Response in ...

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IEEE Annual Joint conference: INFOCOM, IEEE computer and Communications Societies

作者： Jianhai Chen Deshi Ye Shouling Ji Qinming He Yang Xiang Zhenguang Liu Institute of Cyberspace Research and College of Computer Science and Technology Zhejiang University Hangzhou Alibaba-Zhejiang University Joint Institute of Frontier Technologies Hangzhou China Swinburne Research Swinburne University of Technology Victoria Australia Dept. of Computer Science National University of Singapore Singapore

Demand response (DR) is a vital means of electricity market in maintaining power grid reliability, sustainability and stability. DR can enable consumers (e.g. data centers) to reduce their electricity consumption when the supply of electricity is a shortage. The consumers will be rewarded if they reduce or shift some of their energy usage during peak hours. Aiming at solving the efficiency of DR, in this paper, we present MEDR, a mechanism on emergency DR in colocation data center. First, we formalize the MEDR problem and propose a dynamic programming to solve the optimization version of the problem. We then design a deterministic mechanism to solve the MEDR. We prove that our mechanism is truthful and it is an FPTAS, i.e., it can be approximated within 1 + ε for any given ε > 0, while the running time of our mechanism is polynomial in the number of tenants n and 1/ε. Furthermore, we also give an auction system covering the efficient FPTAS algorithm as bidding decision program for DR. Finally, we choose a real dataset to build a large number of simulation datasets in performance evaluation. The results show that our mechanism outperforms near-optimal and high utility demonstrate the effectiveness of our work.

关键词： Data centers Dynamic programming Heuristic algorithms Power grids Optimization Approximation algorithms Load management

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Design improvement of an airbox for a passenger vehicle

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Journal of Physics: conference Series 2021年第1期2120卷

作者： J Tan N Z Abu Bakar School of Computer Science and Engineering Taylor's University Lakeside Campus No. 1 Jalan Taylor's 47500 Subang Jaya Selangor Darul Ehsan Malaysia.

The purpose of an airbox is to provide the engine with a clean air flow for combustion. The high velocity of the fluid flow across the airbox will create a pressure drop resulting a decline in the vehicle's performance. This project collaborates with an Original Equipment Manufacturer (OEM) to develop a numerical simulation model for a new airbox design and to compare its pressure drop with OEM production design. Reducing the pressure drop across the airbox can increase the efficiency of a vehicle, hence, reducing CO2 emissions. This research focuses on the passenger type vehicle as it is the highest source of carbon dioxide (CO2) being emitted for road transportation and these pollutant emissions have also caused many health problems on human. ANSYS Fluent program was used to carry out Computational Fluid Dynamics (CFD) simulation for both OEM and the new design. Then, the same simulation setup was used for the new design. The inlet size of the new design is larger when compared to the OEM design. After analysing both models, it was determined that the main reason behind the pressure loss was caused by the shape of the airbox and turbulent flow inside. The new airbox design shows reduction of 96% in the pressure drop within it and in return, enhancing the performance of the passenger vehicle. This conclude that numerical simulation model is able to provide a good indicator for the designer to choose the best design and proceed with fabrication and conduct actual test, thus saving a lot of prototyping and repeated testing cost.

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