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检索条件"任意字段=Conference on High Performance Computer Modernization Program"

共 10372 条记录，以下是4711-4720 订阅

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HHVSF: A Framework to Accelerate Drug-Based high-Throughput Virtual Screening on high-performance computers 4th

HHVSF: A Framework to Accelerate Drug-Based High-Throughput ...

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4th Asian conference on Supercomputing Frontiers (SCFA)

作者： Chen, Pin Yan, Xin Li, Jiahui Du, Yunfei Xu, Jun Sun Yat Sen Univ Natl Supercomp Ctr Guangzhou 132 East Circle Univ City Guangzhou 510006 Peoples R China Sun Yat Sen Univ Sch Data & Comp Sci Res Ctr Drug Discovery 132 East Circle Univ City Guangzhou 510006 Peoples R China Sun Yat Sen Univ Sch Pharmaceut Sci 132 East Circle Univ City Guangzhou 510006 Peoples R China Natl Univ Def Technol Sch Comp Sci Changsha 410073 Peoples R China

ISBN: (纸本)9783319699530;9783319699523

The high-performance high-throuhput Virtual Screening Framework (HHVSF) has been developed to accelerate high-Throughput Virtual Screening (HTVS) on high-performance computers. Task management and data management are two core components in HHVSF. Fine-grained computing resources are configured to support serial or threaded applications. Each task gets the input file from database through a preemptive algorithm and the failed tasks can be found and corrected. NoSQL database MongoDB is used as the data repository engine. Data is mobilized between the RAMDISK in computing node and the database. Data analysis is carried out after the computing process, and the results are stored in the database. Among the most popular molecular docking and molecular structure similarity packages, Autodock_vina (ADV) and WEGA were chosen to carry out experiments. Results show that when ADV was used for molecular docking, 10 million molecules were screened and analyzed in 22.31 h with 16000 cores, and the throughput reached up to 1324 molecules per second, averaging 145 molecules per second during the steady-running process. For WEGA, 958 million conformations were screened and analyzed in 34.12 min with 4000 cores, of which throughput reached up to 9448 molecules per second, 6430 molecules per second on average.

关键词： high-Throughput Virtual Screening Drug discovery high-performance Computing Molecular docking Molecular structure similarity

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Hybrid Database System of MySQL and MongoDB in Web Application Development 3

Hybrid Database System of MySQL and MongoDB in Web Applicati...

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3rd International conference on Information Management and Technology, ICIMTech 2018

作者： Ongo, Gregorius Kusuma, Gede Putra Computer Science Department Bina Nusantara University BINUS Graduate Program-Master of Computer Science Jakarta11480 Indonesia

ISBN: (纸本)9781538658215

The increasing amount of data that need to be processed in a company are affecting the performances of the database system. Relational Database Management System (RDBMS) is a commonly used database system, but also known to having a decreased performance when handling high amount of data. N oSQL is an alternative storage option that is different than RDBMS and known for faster performance when handling high amount of data. In this contribution, we compare the performances between RDBMS MySQL and a hybrid model of MySQL and NoSQL MongoDB when being used on a web application. We implemented a simple social media website to evaluate the performance of using different database models. The website is equipped with chat and profile view features. Experiments are performed using randomly generated user profiles and chat data. Based on our evaluations, the hybrid database of MySQL and MongoDB achieves higher read and write performances than the MySQL alone. Meanwhile MySQL can handle more sensitive data and maintaining data consistency. The hybrid model database MySQL and MongoDB uses less disk space than MySQL alone, but uses more RAM. We also observed that there is not much difference in CPU usage for both database models. © 2018 IEEE.

关键词： Sensitive data

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Compiler-Based high-Level Synthesis of Application-Specific Processors on FPGAs

Compiler-Based High-Level Synthesis of Application-Specific ...

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International conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Patrick Plagwitz Franz-Josef Streit Andreas Becher Stefan Wildermann Jürgen Teich Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) Germany

ISBN: (纸本)9781728119588

In order to meet tight performance and/or energy constraints of embedded systems, the implementation of applications in hardware is often a must. However, mapping of algorithms to platforms, as for example Field-programmable Gate Arrays (FPGAs), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern high-Level Synthesis (HLS) offers a means to ease the generation of hardware implementations from a software specification of an application. Although these tools have improved greatly in recent years, they often do not provide full coverage of important programming constructs and are therefore of limited use when used with existing or automatically generated code. Soft-core processors implemented with FPGA-logic can circumvent this limitation. However, these come with drawbacks in terms of performance and resource requirements as a general-purpose architecture is used to implement the application in software rather than as a highly specialized circuit. As a remedy, our work presents a novel compiler-based synthesis methodology that generates networks of Application-Specific Instruction Set Processors (ASIPs) from unmodified C/C++ algorithms. We thereby bridge the gap between traditional soft-core processors and HLS. To show the practicability of our approach, we present a case study of a JPEG decoder application while investigating design objectives like resource costs and performance. Apart from the generality of the compiler-based approach, our approach also shows better results in terms of required hardware resources and execution times compared to Instruction Set Architecture (ISA)-fixed commercial Xilinx MicroBlaze soft-cores.

关键词： application specific integrated circuits embedded systems field programmable gate arrays high level synthesis image coding instruction sets microprocessor chips program compilers Field programmable gate arrays high level synthesis application specific integrated circuits instruction sets compilers Microprocessor chips Embedded systems image coding PROCESSOR hardware resource soft-core Application specific processors computer hardware

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An Integrated Load-balancing Scheduling Algorithm for Nginx-Based Web Application Clusters 2

An Integrated Load-balancing Scheduling Algorithm for Nginx-...

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2018 2nd International conference on Data Mining, Communications and Information Technology, DMCIT 2018

作者： Li, Ruoyu Li, Yunchun Li, Wei School of Computer Science and Engineering BeiHang University Beijing China

In recent years, the LXC (Linux Container)-based Docker technology has attracted great attention due to its lightweight and convenient features. Because of the performance differences among the hosts and the network complexity, it's necessary to improve the resource utilization of WEB application clusters. This paper analyzes the WEB application deployment architecture based on container technology, calculates the host load metrics combined the host's performance indicates and status of the operating containers, including CPU utilization, memory utilization, network utilization, and the proportion of unused memory that has been allocated for the containers, and proposes a Dynamic Weighted Least-Connection Algorithm(DWLC). The experiment shows that, the DWLC algorithm helps the WEB application response 52.6% and 46.4% faster than the ordinary Round-Robin and Least-Connection algorithm. © Published under licence by IOP Publishing Ltd.

关键词： Containers

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Salient Object Detection Driven by Fixation Prediction 31

Salient Object Detection Driven by Fixation Prediction

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31st IEEE/CVF conference on computer Vision and Pattern Recognition (CVPR)

作者： Wang, Wenguan Shen, Jianbing Dong, Xingping Borji, Ali Beijing Inst Technol Sch Comp Sci Beijing Lab Intelligent Informat Technol Beijing Peoples R China Incept Inst Artificial Intelligence Abu Dhabi U Arab Emirates Univ Cent Florida Dept Comp Sci Orlando FL 32816 USA

ISBN: (纸本)9781538664209

Research in visual saliency has been focused on two major types of models namely fixation prediction and salient object detection. The relationship between the two, however, has been less explored. In this paper, we propose to employ the former model type to identify and segment salient objects in scenes. We build a novel neural network called Attentive Saliency Network (ASNet) 1 that learns to detect salient objects from fixation maps. The fixation map, derived at the upper network layers, captures a high-level understanding of the scene. Salient object detection is then viewed as fine-grained object-level saliency segmentation and is progressively optimized with the guidance of the fixation map in a top-down manner. ASNet is based on a hierarchy of convolutional LSTMs (convLSTMs) that offers an efficient recurrent mechanism for sequential refinement of the segmentation map. Several loss functions are introduced for boosting the performance of the ASNet. Extensive experimental evaluation shows that our proposed ASNet is capable of generating accurate segmentation maps with the help of the computed fixation map. Our work offers a deeper insight into the mechanisms of attention and narrows the gap between salient object detection and fixation prediction.

关键词： Object detection Task analysis Analytical models computer architecture Computational modeling Predictive models

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Multi-Parameter performance Modeling Based on Machine Learning with Basic Block Features

Multi-Parameter Performance Modeling Based on Machine Learni...

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IEEE International conference on Big Data and Cloud Computing (BdCloud)

作者： Meng Hao Weizhe Zhang Yiming Wang Dong Li Wen Xia Hao Wang Chen Lou School of Computer Science and Technology Harbin Institute of Technology China Cyberspace Security Research Center Peng Cheng Laboratory Shenzhen China Department of Electrical Engineering and Computer Science University of California Merced Department of Computer Science Norwegian University of Science and Technology Norway

ISBN: (数字)9781728143286

ISBN: (纸本)9781728143293

Considering the increasing complexity and scale of HPC architecture and software, the performance modeling of parallel applications on large-scale HPC platforms has become increasingly important. It plays an important role in many areas, such as performance analysis, job management, and resource estimation. In this work, we propose a multi-parameter performance modeling and prediction framework called MPerfPred, which utilizes basic block frequencies as features and uses machine learning algorithms to automatically construct multi-parameter performance models with high generalization ability. To reduce the prediction overhead, we propose some feature-filtering strategies to reduce the number of features in the training stage and build a serial program called BBF collector for each target application to quickly collect feature values in the prediction stage. We demonstrate the use of MPerfPred on the TianHe-2 supercomputer with six parallel applications. Results show that MPerfPred with SVR achieves better prediction than other input parameter-based modeling methods. The average prediction error and average standard deviation of prediction errors of MPerfPred are 8.42% and 6.09%, respectively. In the prediction stage, the average prediction overhead of MPerfPred is less than 0.13% of the total execution time.

关键词： Training Predictive models Machine learning algorithms Machine learning Instruments Data models Prediction algorithms

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6-DOF exit simulations for C-130 H/J airdrop configurations 36th

6-DOF exit simulations for C-130 H/J airdrop configurations

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36th AIAA Applied Aerodynamics conference, 2018

作者： Bergeron, Keith Ghoreyshi, Mehdi Jirasek, Adam US Army Natick Research Development and Engineering Center NatickMA01760 United States High Performance Computing Research Center U.S. Air Force Academy USAF Academy CO80840 United States

ISBN: (纸本)9781624105593

This paper presents preliminary computational simulations of the extraction of a standard container express (CONEX) cargo container from a C-130J. The aircraft configuration includes ramp and flaps deployed and propellers modeled. Static and dynamic time-accurate, unsteady CFD simulations of multiple bodies with both prescribed motion and coupled 6-DOF dynamics were completed. Two dynamic simulations are performed to exercise both the unstructured grid and near-body/off-body capabilities of the DoD HPCMP CREATE™Kestrel software product. The results contribute to a continuing computational effort to understand the flow field characteristics of C-130 Hercules aircraft configured for airdrop operations, and serve as a baseline for future investigations. © 2018, American Institute of Aeronautics and Astronautics Inc, AIAA. All rights reserved.

关键词： Aircraft

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TAMM: A New Topology-Aware Mapping Method for Parallel Applications on the Tianhe-2A Supercomputer 18th

TAMM: A New Topology-Aware Mapping Method for Parallel Appli...

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18th International conference on Algorithms and Architectures for Parallel Processing (ICA3PP)

作者： Chen, Xinhai Liu, Jie Li, Shengguo Xie, Peizhen Chi, Lihua Wang, Qinglin Natl Univ Def Technol Sci & Technol Parallel & Distributed Proc Lab Changsha 410073 Peoples R China Hunan Inst Traff Engn Inst Adv Sci & Technol Hengyang 421001 Peoples R China

ISBN: (纸本)9783030050511;9783030050504

With the increasing size of high performance computing systems, the expensive communication overhead between processors has become a key factor leading to the performance bottleneck. However, default process-to-processor mapping strategies do not take into account the topology of the interconnection network, and thus the distance spanned by communication messages may be particularly far. In order to enhance the communication locality, we propose a new topology-aware mapping method called TAMM. By generating an accurate description of the communication pattern and network topology, TAMM employs a two-step optimization strategy to obtain an efficient mapping solution for various parallel applications. This strategy first extracts an appropriate subset of all idle computing resources on the underlying system and then constructs an optimized one-to-one mapping with a refined iterative algorithm. Experimental results demonstrate that TAMM can effectively improve the communication performance on the Tianhe-2A supercomputer.

关键词： high performance computing systems Topology-aware mapping Communication pattern Network topology

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An Efficient Data Reuse Strategy for Multi-Pattern Data Access 18

An Efficient Data Reuse Strategy for Multi-Pattern Data Acce...

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37th IEEE/ACM International conference on computer-Aided Design (ICCAD)

作者： Li, Wensong Yang, Fan Zhu, Hengliang Zeng, Xuan Zhou, Dian Fudan Univ Sch Microelect State Key Lab ASIC & Syst Shanghai Peoples R China Univ Texas Dallas Dept Elect Engn Richardson TX 75083 USA

ISBN: (纸本)9781450359504

Memory partitioning has been widely adopted to increase the memory bandwidth. Data reuse is a hardware-efficient way to improve data access throughput by exploiting locality in memory access patterns. We found that fitr many applications in image and video processing, a global data reuse scheme can be shared by multiple patterns. In this paper, we propose an efficient data reuse strategy for multi-pattern data access. Firstly, a heuristic algorithm is proposed to extract the reuse information as well as find the non-reusable data elements of each pattern. Then the non-reusable elements are partitioned into several memory banks by an efficient memory partitioning algorithm. Moreover, the reuse information is utilized to generate the global data reuse logic shared by the multi-pattern. We design a novel algorithm to minimize the number of registers required by the data reuse logic. Experimental results show that compared with the state-of-the-art approach, our proposed method can reduce the number of required BRAMs by 62.2% on average, with the average reduction of 82.1% in SLICE, 87.1% in LUTs, 71.6% in Flip-Flops, 73.170 in DSP48Es, 83.8% in SRLs, 46.77 in storage overhead, 79.1% in dynamic power consumption, and 82.6% in execution time of memory partitioning. Besides, the performance is improved by 14.4%.

关键词： Data Reuse Memory Partition Parallel Data Access high-Level Synthesis

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Development of a Continuous Complex Event Processing Platform for Real-Time Tactical Moving Objects

Development of a Continuous Complex Event Processing Platfor...

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IEEE International conference on Big Data

作者： Jiwan Lee Bonghee Hong Chumsoo Kim Woo Chan Kim BK21PLUS Creative Human Resource Development Program for IT Convergence Pusan National University Busan South Korea Department of Electrical and Computer Engineering Pusan National University Busan South Korea Agency for Defense Development South Korea

ISBN: (数字)9781728108582

ISBN: (纸本)9781728108599

This paper designs a rule-based complex event processing platform that processes rules for processing sensor data streams differently depending on the front, back, and sides of the naval vessel. The complex event processing platform supports event filtering rules, event capturing rules, continuous queries rules, and complex event processing rules. To support the high-performance rule-based complex event processing, our platform implements continuous query indexing, CEP index, and Rete algorithm.

关键词： Data processing Query processing Real-time systems Knowledge based systems Graphical user interfaces Information filtering

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