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检索条件"任意字段=Conference on High Performance Computer Modernization Program"

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Egeria: A Framework for Automatic Synthesis of HPC Advising Tools through Multi-Layered Natural Language Processing 17

Egeria: A Framework for Automatic Synthesis of HPC Advising ...

引用

International conference for high performance Computing, Networking, Storage and Analysis (SC)

作者： Guan, Hui Shen, Xipeng Krim, Hamid North Carolina State Univ Raleigh NC 27695 USA

ISBN: (数字)9781450351140

ISBN: (纸本)9781450351140

Achieving high performance on modern systems is challenging. Even with a detailed profile from a performance tool, writing or refactoring a program to remove its performance issues is still a daunting task for application programmers: it demands lots of program optimization expertise that is often system specific. Vendors often provide some detailed optimization guides to assist programmers in the process. However, these guides are frequently hundreds of pages long, making it difficult for application programmers to master and memorize all the rules and guidelines and properly apply them to a specific problem instance. In this work, we develop a framework named Egeria to alleviate the difficulty. Through Egeria, one can easily construct an advising tool for a certain high performance computing (HPC) domain (e.g., GPU programming) by providing Egeria with a optimization guide or other related documents for the target domain. An advising tool produced by Egeria provides a concise list of essential rules automatically extracted from the documents. At the same time, the advising tool serves as a question-answer agent that can interactively offers suggestions for specific optimization questions. Egeria is made possible through a distinctive multi-layered design that leverages natural language processing techniques and extends them with knowledge of HPC domains and how to extract information relevant to code optimization Experiments on CUDA, OpenCL, and Xeon Phi programming guides demonstrate, both qualitatively and quantitatively, the usefulness of Egeria for HPC.

关键词： program optimization high performance computing natural language processing

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performance Guaranteed Network Acceleration via high-Order Residual Quantization 16

Performance Guaranteed Network Acceleration via High-Order R...

引用

16th IEEE International conference on computer Vision (ICCV)

作者： Li, Zefan Ni, Bingbing Zhang, Wenjun Yang, Xiaokang Gao, Wen Shanghai Jiao Tong Univ Shanghai Peoples R China Peking Univ Beijing Peoples R China

ISBN: (纸本)9781538610329

Input binarization has shown to be an effective way for network acceleration. However, previous binarization scheme could be regarded as simple pixel-wise thresholding operations (i.e., order-one approximation) and suffers a big accuracy loss. In this paper, we propose a high-order binarization scheme, which achieves more accurate approximation while still possesses the advantage of binary operation. In particular, the proposed scheme recursively performs residual quantization and yields a series of binary input images with decreasing magnitude scales. Accordingly, we propose high-order binary filtering and gradient propagation operations for both forward and backward computations. Theoretical analysis shows approximation error guarantee property of proposed method. Extensive experimental results demonstrate that the proposed scheme yields great recognition accuracy while being accelerated.

关键词： Quantization (signal) Tensile stress Acceleration Training Convolution Neural networks Approximation algorithms

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DAWS: Exploiting Crossbar Characteristics for Improving Write performance of high Density Resistive Memory 35

DAWS: Exploiting Crossbar Characteristics for Improving Writ...

引用

35th IEEE International conference on computer Design (ICCD)

作者： Wang, Chengning Feng, Dan Liu, Jingning Tong, Wei Wu, Bing Zhang, Yang Huazhong Univ Sci & Technol Minist Educ China Sch Comp Sci & Technol Wuhan Natl Lab OptoelectKey Lab Informat Storage Wuhan Hubei Peoples R China

ISBN: (纸本)9781538622544

Resistive random access memory (RRAM) is promising to be used as high density storage-class memory by employing crossbar structure. However, the wire resistance in crossbar array causes the IR drop problem, which makes nonuniformity of write latency throughout the array. In large crossbar array, the write latency differs greatly even in the same row. Since the write latency of a region is determined by its slowest write-unit, the conventional group-by-row region partition and addressing scheme is suboptimal for improving the overall performance of RRAM. In this work, we present DAWS, a novel RRAM architecture that exploits intrinsic features of crossbar structure. We first build a circuit model to analyze the voltage distribution and write latency distribution in a crossbar array. Then we propose a voltage bias scheme to optimize write latency via minimizing the IR drop path. We further present block diagonal partition to narrow the variance of write latency within each region, thus the write latency of each region is reduced. Moreover, we provide block diagonal addressing to make the write latency monotonically increase with the physical address, which is in favor of address mapping and memory allocation. We also design diagonal writing and diagonal swapping to overlap SET and RESET operations by applying a particular voltage bias pattern that can exploit row level parallelism, thus the number of write operations is halved. The experimental results show that DAWS can reduce memory access latency by 24.0% and improve system performance by 29.7% over an aggressive baseline.

关键词： computer architecture Microprocessors Wires Resistance Mathematical model Switches Random access memory

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Change-Aware Dynamic program Analysis for JavaScript

Change-Aware Dynamic Program Analysis for JavaScript

引用

International conference on Software Maintenance (ICSM)

作者： Dileep Ramachandrarao Krishna Murthy Michael Pradel Department of Computer Science TU Darmstadt Darmstadt Germany

Dynamic analysis is a powerful technique to detect correctness, performance, and security problems, in particular for programs written in dynamic languages, such as JavaScript. To catch mistakes as early as possible, developers should run such analyses regularly, e.g., by analyzing the execution of a regression test suite before each commit. Unfortunately, the high overhead of these analyses make this approach prohibitively expensive, hindering developers from benefiting from the power of heavyweight dynamic analysis. This paper presents change-aware dynamic program analysis, an approach to make a common class of dynamic analyses change-aware. The key idea is to identify parts of the code affected by a change through a lightweight static change impact analysis, and to focus the dynamic analysis on these affected parts. We implement the idea based on the dynamic analysis framework Jalangi and evaluate it with 46 checkers from the DLint and JITProf tools. Our results show that change-aware dynamic analysis reduces the overall analysis time by 40%, on average, and by at least 80% for 31% of all commits.

关键词： performance analysis Tools Runtime Reactive power Dynamic programming

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Placement Solution For Homogeneous FPGA Using Tree-based Algorithm

Placement Solution For Homogeneous FPGA Using Tree-based Alg...

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International conference on Computing Communication Control and Automation

作者： Ashish kumar Department of Computer Science and Engineering NIT Silchar Silchar INDIA

ISBN: (纸本)9781538652589;9781538652572

Nowadays, FPGA Placement problems have become more complicated since they need to account area constraint and time constraint. Placement is still one of the most difficult problems as the FPGA designs become larger and more complex. As FPGAs are programmable in nature they are an ideal fit for many different markets such as Aerospace, Defense, Audio, Automotive, Broadcast, Industrial, Medical, Security, Video & Image Processing, Wired & Wireless communications. Also, FPGA is becoming popular among big companies and researchers who apply FPGA to high-performance computing and deep learning as it provides better performance, flexible programmability, better cost, etc. In this paper, we present a Tree-based placement algorithm for Homogeneous FPGAs. By applying our algorithm on a set of benchmark circuits we have effectively reduced the placement cost. We have compared results with VPR that uses Simulated annealing approach and our results are comparatively better.

关键词： Field programmable gate arrays Partitioning algorithms program processors Simulated annealing computer architecture Cost function Wires

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An Improved Changing-Topology Moving Mesh Method in OpenFOAM 6

An Improved Changing-Topology Moving Mesh Method in OpenFOAM

引用

6th IEEE International conference on computer, Information and Telecommunication Systems (IEEE CITS)

作者： Wang, Jinyu Xu, Xinhai Li, Chao Tang, Yuhua Natl Univ Def Technol Coll Comp State Key Lab High Performance Comp Changsha Hunan Peoples R China

ISBN: (纸本)9781509059577

In this paper, an improved changing-topology moving mesh method is developed in OpenFOAM (a widely used CFD software) to solve the moving boundary problem. We use mesh smoothing and edge swapping to improve the mesh quality, together with edge bisection and edge contraction to control the mesh resolution. In order to increase the mesh motion efficiency, a local refinement algorithm is realized. In addition, to ensure the regenerated mesh quality is higher than the original mesh, an improved checking algorithm is implemented during the mesh motion. The effectiveness of our method is demonstrated by simulations of the NACA0012 airfoil with translation, rotation and fish-like undulating locomotion.

关键词： Moving mesh Local refinement Edge swapping

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Developments of the MICHELLE charged particle beam optics code for high performance computing 18

Developments of the MICHELLE charged particle beam optics co...

引用

18th International Vacuum Electronics conference (IVEC)

作者： Petillo, John Ovtchinnikov, Serguei Kostas, Chris Panagos, Dimitrios Jensen, Aaron Burke, Alex Nelson, Eric Stantchev, George Cooke, Simon Held, Ben Nichols, Alan Ayala, Sreeram Leidos Corp Billerica MA 01820 USA US Naval Res Lab Washington DC 20375 USA AWR Natl Instruments Mequon WI 53092 USA

ISBN: (纸本)9781509059164

The existing HPC capabilities in the MICHELLE ES PIC code is being supplanted with new distributed-memory, MPI-based domain decomposition and per-node accelerators such as GPUs and multicore processing. New interfaces are also being built between MICHELLE and existing DOD software tools such as CAPSTONE, GSB, and ParaView to form the next generation framework for efficient design and optimization workflow. This is an evolutionary process, and this paper reports on the latest progress and discusses applicable algorithms and implementations.

关键词： MICHELLE electron optics electron gun code HPC GPU domain decomposition multicore multithreading CAPSTONE GSB

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Enabling Adaptive Loop Pipelining in high-Level Synthesis 51

Enabling Adaptive Loop Pipelining in High-Level Synthesis

引用

51st IEEE Annual Asilomar conference on Signals, Systems, and computers

作者： Dai, Steve Liu, Gai Zhao, Ritchie Zhang, Zhiru Cornell Univ Sch Elect & Comp Engn Ithaca NY 14850 USA

ISBN: (纸本)9781538618233

Loop pipelining is an important optimization in high-level synthesis (HLS) because it allows successive loop iterations to be overlapped during execution. While current HLS pipelining approach achieves high performance for loops with regular and statically analyzable program patterns, it remains challenging to pipeline loops with irregular memory accesses, irregular dependence patterns, and unbalanced workload. The lack of support for dynamic program behaviors results in conservatively synthesized pipelines that sacrifice performance for maintaining presumed regularity. In this paper, we survey some of our recent work that addresses these challenges using a coordinated dynamic-static approach for enabling high-throughput pipelining of irregular loops. We propose to augment the HLS pipeline with dynamic scheduling to adapt to data-dependent behaviors, while employing static compile-time optimizations to minimize the hardware overhead associated with runtime optimization. Experimental results demonstrate that our proposed techniques can significantly improve effective pipeline throughput while conserving hardware resources.

关键词： high level synthesis

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Fast-Reconfigurable Optical Interconnect Architecture Based on Time-Synchronized Node Coordination for high performance Computing

Fast-Reconfigurable Optical Interconnect Architecture Based ...

引用

Asia Communications and Photonics conference (ACP)

作者： Yu, Yufang Hua, Nan Zhong, Zhizhen Li, Jialong Luo, Ruijie Zheng, Zelin Zheng, Xiaoping Tsinghua Univ Dept Elect Engn TNList Beijing 100084 Peoples R China

We propose a Fast-Reconfigurable Optical Interconnect (FROI) architecture enabled by time-synchronized node coordination for high perfounance computing. Experimental results show that an ultra-low reconfiguration time... 详细信息

ISBN: (纸本)9781943580347

关键词： Traffic control Optical switches Optical interconnections Resource management Routing computer architecture high performance computing

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Generalized Buffer-State-Based Relay Selection with Collaborative Beamforming

Generalized Buffer-State-Based Relay Selection with Collabor...

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作者： Nakai, Ryota Oiwa, Miharu Lee, Kyungchun Sugiura, Shinya Department of Computer Information Sciences Tokyo University of Agriculture and Technology Koganei184-8588 Japan Department of Electrical Information Engineering Seoul National University Science and Technology Seoul01811 Korea Republic of

In this paper, we propose a generalized buffer-state-based relaying protocol in the context of finite buffer-aided cooperative systems. The proposed relaying scheme relies on two concepts: the simultaneous activation of multiple source-to-relay links and buffer-state-based relay selection for packet transmission and reception. In order to avoid buffer overflow, as well as an empty buffer at the relay nodes, we introduce a novel thresholding scheme that gives priority to link selection. The proposed scheme is capable of achieving a lower outage probability and a lower end-to-end packet delay than existing buffer-aided relaying protocols. Moreover, the concept of collaborative beamforming is invoked for the proposed buffer-aided relaying scheme, in order to improve the received signal-to-noise ratio at the destination node. We also derive analytical bounds of the outage probability and the average packet delay of the proposed scheme with the aid of Markov-chain analysis. Our simulation results demonstrate the clear performance advantages of the proposed scheme over conventional schemes, which are especially explicit for scenarios with a high number of relay nodes. © 1967-2012 IEEE.

关键词： Beamforming

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