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检索条件"任意字段=Conference on High Performance Computer Modernization Program"

共 10372 条记录，以下是4981-4990 订阅

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SSTI and its mitigation in wind farms connected with an HVDC line 8th

SSTI and its mitigation in wind farms connected with an HVDC...

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8th International conference on Advances in Information Technology (IAIT)

作者： Qu, Wenhui Jiang, Jianguo Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai 200240 Peoples R China

Frequent oscillation occurs at the wind farms of Santanghu District, which are connected to a +/- 800 kV high voltage direct current line (HVDC). After analysis of the oscillation frequency and its characteristics, it is concluded that the oscillation occurs because of subsynchronous torsional interaction (SSTI) caused by the interaction between the wind turbine generators and the HVDC link. To suppress the SSTI phenomenon, an additional SSTI stabilizer is proposed and installed in Wind Farm 1 of Santanghu. The additional SSTI stabilizer exhibits good performance in mitigating oscillation, with the advantage of low cost and a low additional area footprint. (C) 2017 The Authors. Published by Elsevier B.V.

关键词： subsynchronous torsional interaction high voltage direct current wind farms stability

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Investigation on measurement for micro unbalance of tiny cylindrical rollers of the high-speed precision rolling bearings 2

Investigation on measurement for micro unbalance of tiny cyl...

引用

2nd International conference on Mechanical, Control and computer Engineering (ICMCCE)

作者： Wang, Xiao Li, Jishun Sui, Xin Ma, Wei Xue, Yujun Liu, Chunyang Henan Univ Sci & Technol Sch Mechatron Engn Luoyang 471003 Peoples R China Henan Univ Sci & Technol Henan Key Lab Machinery Design & Transmiss Syst Luoyang 471003 Peoples R China

ISBN: (纸本)9781538626283

As one of the critical infrastructure components in modern industry, the high-speed precision rolling bearings are widely equipped on high-end advanced equipment. It is stringent requirement for China to develop the precision measurement technology about how to measure the unavoidable micro residual unbalance of the bearings' tiny cylindrical rollers, which seriously affects the performance and service life of high-speed precision rolling bearings. A tiny cylindrical roller is a rotor without shaft which cannot be mounted at rotor-bearing systems directly and the vibration response excited by micro unbalance is difficult to be detected and easy to be messed up with background noise. To make the precision measurement feasible, a soft support mounting bracket is designed. To measure the mu m amplitude of vibration of mounting bracket, a high precision laser-based non-contact measurement system consisting of a roller rotation drive system, a vibration signal acquisition system and a signal process system are developed as well. Finally, the validity of the proposed measurement system is verified by comparing the measurement results of a standard roller and a special prepared unbalanced roller.

关键词： Micro Unbalance Measurement Tiny Cylindrical Roller high-speed Precision Rolling Bearings

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Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time Multicores 35

Decomposed Task Mapping to Maximize QoS in Energy-Constraine...

引用

35th IEEE International conference on computer Design (ICCD)

作者： Mo, Lei Kritikakou, Angeliki Sentieys, Olivier INRIA IRISA Rennes France Univ Rennes 1 Rennes France

ISBN: (纸本)9781538622544

Multicore architectures are now widely used in energy-constrained real-time systems, such as energy-harvesting wireless sensor networks. To take advantage of these multicores, there is a strong need to balance system energy, performance and Quality-of-Service (QoS). The Imprecise Computation (IC) model splits a task into mandatory and optional parts allowing to tradeoff QoS. The problem of mapping, i.e. allocating and scheduling, IC-tasks to a set of processors to maximize system QoS under real-time and energy constraints can be formulated as a Mixed Integer Linear programming (MILP) problem. However, state-of-the-art solving techniques either demand high complexity or can only achieve feasible (suboptimal) solutions. In this paper, we develop an effective decomposition-based approach to achieve an optimal solution while reducing computational complexity. It decomposes the original problem into two smaller easier-to-solve problems: a master problem for IC-tasks allocation and a slave problem for IC-tasks scheduling. We also provide comprehensive optimality analysis for the proposed method. Through the simulations, we validate and demonstrate the performance of the proposed method, resulting in an average 55% QoS improvement with regards to published techniques.

关键词： Quality of service Resource management program processors Processor scheduling Manganese Linear programming

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Fast Linear Algebra-Based Triangle Counting with KokkosKernels

Fast Linear Algebra-Based Triangle Counting with KokkosKerne...

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IEEE high performance Extreme Computing conference (HPEC)

作者： Wolf, Michael M. Deveci, Mehmet Berry, Jonathan W. Hammond, Simon D. Rajamanickam, Sivasankaran Sandia Natl Labs Ctr Res Comp POB 5800 Albuquerque NM 87185 USA

ISBN: (纸本)9781538634721

Triangle counting serves as a key building block for a set of important graph algorithms in network science. In this paper, we address the IEEE HPEC Static Graph Challenge problem of triangle counting, focusing on obtaining the best parallel performance on a single multicore node. Our implementation uses a linear algebra-based approach to triangle counting that has grown out of work related to our miniTri data analytics miniapplication [1] and our efforts to pose graph algorithms in the language of linear algebra. We leverage KokkosKernels to implement this approach efficiently on multicore architectures. Our performance results are competitive with the fastest known graph traversal-based approaches and are significantly faster than the Graph Challenge reference implementations, up to 670,000 times faster than the C++ reference and 10,000 times faster than the Python reference on a single Intel Haswell node.

关键词： Sparse matrices Algorithm design and analysis Linear algebra C++ languages Kernel Libraries computer architecture

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ParaView + Alya+D8tree: Integrating high performance Computing and high performance Data Analytics

ParaView + Alya+D8tree: Integrating High Performance Computi...

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International conference on Computational Science (ICCS)

作者： Artigues, Antoni Cugnasco, Cesare Becerra, Yolanda Cucchietti, Fernando Houzeaux, Guillaume Vazquez, Mariano Torres, Jordi Ayguade, Eduard Labarta, Jesus Barcelona Supercomp Ctr Barcelona Catalonia Spain Univ Politecn Cataluna Dept Comp Architecture Barcelona Spain IIIA CSIC Bellaterra Spain

Large scale time-dependent particle simulations can generate massive amounts of data, making it so that storing the results is often the slowest phase and the primary time bottleneck of the simulation. Furthermore, analysing this amount of data with traditional tools has become increasingly challenging, and it is often virtually impossible to have a visual representation of the full set. We propose a novel architecture that integrates an HPC-based multi-physics simulation code, a NoSQL database, and a data analysis and visualisation application. The goals are two: On the one hand, we aim to speed up the simulations taking advantage of the scalability of key-value data stores, while at the same time enabling real-time approximated data visualisation and interactive exploration. On the other hand, we want to make it efficient to explore and analyse the large data base of results produced. Therefore, this work represents a clear example of integrating high performance Computing with high performance Data Analytics. Our prototype proves the validity of our approach and shows great performance improvements. Indeed, we reduced by 67.5% the time to store the simulation while we made real-time queries run 52 times faster than alternative solutions. (C) 2017 The Authors. Published by Elsevier B.V. Peer-review under responsibility of the scientific committee of the International conference on Computational Science

关键词： HPC HPDA Key-Value data stores

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Accelerating Viterbi Algorithm using Custom Instruction Approach

Accelerating Viterbi Algorithm using Custom Instruction Appr...

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IEEE/ASME International conference on Mechtronic and Embedded Systems and Applications, MESA

作者： Waqar Ahmad Imran Hafeez Abbassi Usman Sanwal Hasan Mahmood Electrical and Computer Engineering Concordia University Montrèal Canada School of Electrical Engineering and Computer Science National University of Sciences and Technology Islamabad Pakistan Computational Biomodeling Laboratory Department of Computer Science Åbo Akademi University Turku Finland Department of Electronics Quaid-i-Azam University Islamabad Pakistan

In recent years, the decoding algorithms in communication networks are becoming increasingly complex aiming to achieve high reliability in correctly decoding received messages. These decoding algorithms involve computationally complex operations requiring high performance computing hardware, which are generally expensive. A cost-effective solution is to enhance the Instruction Set Architecture (ISA) of the processors by creating new custom instructions for the computational parts of the decoding algorithms. In this paper, we propose to utilize the custom instruction approach to efficiently implement the widely used Viterbi decoding algorithm by adding the assembly language instructions to the ISA of DLX, PicoJava II and NIOS II processors, which represent RISC, stack and FPGA-based soft-core processor architectures, respectively. By using the custom instruction approach, the execution time of the Viterbi algorithm is significantly improved by approximately 3 times for DLX and PicoJava II, and by 2 times for NIOS II.

关键词： program processors Viterbi algorithm Convolutional codes Maximum likelihood decoding Field programmable gate arrays computer architecture

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OpenCL-Based Design Pattern for Line Rate Packet Processing 28

OpenCL-Based Design Pattern for Line Rate Packet Processing

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28th IEEE International conference on Application-specific Systems, Architectures and Processors (ASAP)

作者： Khan, Jehandad Athanas, Peter Booth, Skip Marshall, John Virginia Tech NSF Ctr High Performance Reconfigurable Comp CHRE Blacksburg VA 24061 USA Cisco Syst Inc Res Triangle Pk NC USA

ISBN: (纸本)9781509048250

The ever changing nature of network technology requires a flexible platform that can change as the technology evolves. In this work, a complete networking switch designed in OpenCL is presented, identifying several high-level constructs that form the building blocks of any network application targeting FPGAs. These include the notion of an on-chip global memory and kernels constantly processing data without the intervention of the host. The use of OpenCL is motivated by the ability to rapidly change designs and to be maintainable by a wider developer community. Pieces of the design that cannot be realized using current OpenCL technology are also identified and a solution to the problem is presented.

关键词： Kernel Field programmable gate arrays Switches Servers Parallel processing Throughput Architecture

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HybridFS - A high performance and Balanced File System Framework with Multiple Distributed File Systems 41

HybridFS - A High Performance and Balanced File System Frame...

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41st IEEE Annual computer Software and Applications conference (COMPSAC)

作者： Zhang, Lidong Wu, Yongwei Xue, Ruini Hsu, Tse-Chuan Yang, Hongji Chung, Yeh-Ching Tsinghua Univ Grad Sch Shenzhen Shenzhen 518057 Peoples R China Tsinghua Univ TNLIST Dept Comp Sci & Technol Beijing 100084 Peoples R China Tsinghua Univ Res Inst Shenzhen 518057 Peoples R China Univ Elect Sci & Technol Chengdu Sichuan Peoples R China BathSpa Univ Ctr Creat Comp Bath Avon England

ISBN: (纸本)9781538603673

In the big data era, the distributed file system is getting more and more significant due to the characteristics of its scale-out capability, high availability, and high performance. Different distributed file systems may have different design goals. For example, some of them are designed to have good performance for small file operations, such as GlusterFS, while some of them are designed for large file operations, such as Hadoop distributed file system. With the divergence of big data applications, a distributed file system may provide good performance for some applications but fails for some other applications, that is, there has no universal distributed file system that can produce good performance for all applications. In this paper, we propose a hybrid file system framework, HybridFS, which can deliver satisfactory performance for all applications. HybridFS is composed of multiple distributed file systems with the integration of advantages of these distributed file systems. In HybridFS, on top of multiple distributed file systems, we have designed a metadata management server to perform three functions: file placement, partial metadata store, and dynamic file migration. The file placement is performed based on a decision tree. The partial metadata store is performed for files whose size is less than a few hundred Bytes to increase throughput. The dynamic file migration is performed to balance the storage usage of distributed file systems without throttling performance. We have implemented HybridFS in java on eight nodes and choose Ceph, HDFS, and GlusterFS as designated distributed file systems. The experimental results show that, in the best case, HybridFS can have up to 30% performance improvement of read/write operations over a single distributed file system. In addition, if the difference of storage usage among multiple distributed file systems is less than 40%, the performance of HybridFS is guaranteed, that is, no performance degradation.

关键词： Metadata

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DAAIP: Deadblock Aware Adaptive Insertion Policy for high performance Caching 35

DAAIP: Deadblock Aware Adaptive Insertion Policy for High Pe...

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35th IEEE International conference on computer Design (ICCD)

作者： Newton Mahto, Sujit Kr Pai, Suhit Singh, Virendra Indian Inst Technol Dept Elect Engn Comp Architecture & Dependable Syst Lab Bombay Maharashtra India

ISBN: (纸本)9781538622544

The commonly used LRU replacement policy for management of shared last-level cache (LLC) is not efficient as the policy is sharing-oblivious. LRU policy is suitable for applications which show a high-degree of data locality i. e. applications which are cache-friendly. However, applications with working data set greater than the available cache size or poor temporal locality perform poorly with LRU as most of the cache lines inserted by them simply traverse from MRU to LRU position without being re-referenced. Such applications are streaming in their cache behaviour and have very less data reuse. LRU policy makes inefficient use of shared caches for application mixes which are a combination of cache-friendly and streaming applications as the policy treats each cache line independently and doesn't learn from application's past cache reuse behaviour. We show that simple adaptive changes to the insertion policy can significantly improve system's performance. We propose Deadblock Aware Adaptive Insertion Policy (DAAIP) which dynamically adapts to the changing cache behaviour of applications sharing the LLC. DAAIP protects the data of application having high temporal locality from high access rate thrashing/streaming applications. Our proposed mechanism monitors each application at-runtime using cost-effective hardware circuits. The information collected is used to dynamically modify the insertion policy and implicitly partition the cache in favour of application showing more data locality. Our evaluation, with 39 multiprogrammed workloads, shows that DAAIP improves performance of dual-core system by up to 21% and on an average 5.8% over LLC caches managed by SRRIP replacement policy. We show that DAAIP also outperforms state-of-the-art cache replacement policy ABRip by 4.6% on system throughput metric.

关键词： Benchmark testing Adaptive systems program processors Interference System performance System-on-chip Hardware

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Improving the Energy Efficiency for Parallel Applications Running on Clusters 4

Improving the Energy Efficiency for Parallel Applications Ru...

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4th IEEE International conference on Cyber Security and Cloud Computing, CSCloud 2017 and 3rd IEEE International conference of Scalable and Smart Cloud, SSC 2017

作者： Liu, Weifeng Gong, Bin Guo, Meng School of Information Science and Engineering University of Jinan Jinan China Shandong Computer Science Center National Supercomputer Center in Jinan Shandong Provincial Key Laboratory of Computer Networks China

ISBN: (纸本)9781509066438

Now cloud computing is rapidly growing as an alternative to traditional computing architecture. However, it is based on models like cluster computing in general. Thus, improving the energy consumption of the cluster system is the basis for the green cloud. In order to reach exascale computing, more and more efforts are made to improve the energy consumption and efficiency in high performance computing systems. As the de facto standard for designing parallel applications in cluster environment, the Message Passing Interface has been widely used in high performance computing. Therefore, getting the energy consumption information of MPI applications is critical for improving the energy efficiency of cluster systems. By creating a distributed measuring framework which can collect all nodes' energy consumption without the aid of power meters, it is possible to get the detailed energy information of an MPI application. In this work, we present MEMT, a software framework that eases the energy collection in cluster environment. Using this tool, it is viable to find out parameters that affect an MPI program's energy efficiency and to build the models for execution time and energy consumption. Based on the pre-built models, energy saving strategy can be designed. The use of this tool is tested in a cluster. © 2017 IEEE.

关键词： Energy efficiency

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