Energy efficient designs are need of the hour and imageprocessing applications are error tolerant application. Where the error present in the computing does not impact the output visual quality. This work proposes an...
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For the purpose of reducing financial losses and environmental impacts, food waste detection is essential. Inorder to detect food waste using imageprocessing, this study investigates the efficiency of several machine...
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National traditional culture and traditional technology are the products of historical precipitation and indispensable precious resources. The establishment of national cultural database is of great significance for t...
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This study focuses on the design and implementation of an artificial intelligence-driven robotic image perception system, aimed at enhancing robots' visual perception capabilities in complex environments. By explo...
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Generative Adversarial Networks are employed by GAN-based models in image steganography to efficiently conceal information from images while preserving their visual integrity. These models are made up of two primary p...
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Video denoising for raw image has always been the difficulty of camera imageprocessing. On the one hand, image denoising performance largely determines the image quality;moreover, denoising effect in raw image will a...
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Video denoising for raw image has always been the difficulty of camera imageprocessing. On the one hand, image denoising performance largely determines the image quality;moreover, denoising effect in raw image will affect the accuracy of the following operations of ISP processing flow. On the other hand, compared with image, video has motion information in time sequence;thus, motion estimation which is complex and computationally expensive is needed in video denoising. In view of the above problems, this paper proposes a video denoising algorithm for raw image, performing multiple cascading processing stages on raw-RGB image based on convolutional neural network, and carries out implicit motion estimation in the network. The denoising performance is far superior to that of traditional algorithms with minimal computation and bandwidth, and has computational advantages compared with most deep learning algorithms.
Deep learning algorithms are robust to a small amount of noise in the input image. Traditionally, image signal processors (ISP) are used with the CMOS image sensor (CIS) to enhance image quality which consume addition...
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ISBN:
(纸本)9798350387186;9798350387179
Deep learning algorithms are robust to a small amount of noise in the input image. Traditionally, image signal processors (ISP) are used with the CMOS image sensor (CIS) to enhance image quality which consume additional energy and latency. Here, we evaluate an ISP-less CIS architecture in the presence of noise and other in-pixel circuit non-idealities for the autonomous driving application. By integrating the in-pixel processing circuits to CIS, we filter out the redundant frames and only pass the critical bit information downstream to the backend processor. Such in-pixel processing does not allow ISP operations to be applied to the captured raw image. To reflect these limitations, we model and apply circuit non-idealities to the regenerated artificial raw images as an input to the QDTrack network for multi-object tracking. We evaluate the accuracy loss on the BDD100K dataset and examine its sensitivity on each of the imageprocessing steps. We observe an overall accuracy drop of less than 1.2% in Identification F1-score (IDF1) and 2.1% in Multi-Object Tracking Accuracy (MOTA), suggesting that an ISP-less in-pixel processing circuit is feasible to reject 40% redundant frames directly on CIS.
Embedded systems typically require the transmission of significant amounts of data to small-scale CPUs for applications such as radar signal processing, imageprocessing, and embedded AI. Ensuring data integrity durin...
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ISBN:
(纸本)9798350377217;9798350377200
Embedded systems typically require the transmission of significant amounts of data to small-scale CPUs for applications such as radar signal processing, imageprocessing, and embedded AI. Ensuring data integrity during transmission is typically managed using Cyclic Redundancy Check (CRC) algorithms. However, achieving real-time CRC calculation and data storage poses challenges, often necessitating large FIFO memories and multiple clock domains. These additional resources involve a greater hardware complexity. This paper presents an approach aimed at synchronizing the CPU frequency with data transmission. This enables having a single clock domain and a reduction of power consumption. Using hardware/software co-design, it is possible to achieve real-time data storage and CRC calculation without data loss and with a low power consumption.
Division is one of the most commonly sort after algorithm for performing imageprocessing operations such as normalization, filtering, enhancement, deconvolution etc. Hence, the design of efficient division algorithm ...
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Medical image segmentation plays a pivotal role in computer-aided diagnosis by facilitating the extraction of essential features necessary for disease detection and treatment strategies. The continuous progress in ima...
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