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检索条件"任意字段=Conference on Parallel Processing for Imaging Applications"

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Realization of a dynamically reconfigurable preprocessor

Realization of a dynamically reconfigurable preprocessor

引用

IEEE National conference on Aerospace and Electronics (NAECON)

作者： R.B. Lazarus F.M. Meyer TASC Inc. Reading MA USA Wright Laboratories OH USA

Our research demonstrates the feasibility of employing field programmable gate arrays (FPGAs) to realize high-speed algorithm-specific processing architectures for avionic signal processing applications. Architectures composed of FPGAs provide a low-cost and flexible alternative to custom hard-wired preprocessors and a lower-cost, physically smaller alternative to massively parallel processors (both SIMD and MIMD machines). Algorithm segments which require processing hundreds of millions of operations per second have been mapped into a single FPGA device. This technology may ultimately fill a range of processing requirements in the areas of radar and communication processing as well as image enhancement applications. The application of configurable logic devices allows realization of processing architectures to efficiently compute low-level algorithmic functions, or segments. Reconfiguration of FPGAs to implement several algorithm segments is analogous to selecting subroutines to form a software algorithm suite in a conventional processor, since it can be accomplished without hardware modification.< >

关键词： Signal processing algorithms Field programmable gate arrays Image segmentation Application software Software algorithms Aerospace electronics Array signal processing Radar applications Radar imaging Image enhancement

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A serial/parallel color matrix, 2D convolution and 9-Tap filter ASIC with a systems perspective 5

A serial/parallel color matrix, 2D convolution and 9-Tap fil...

引用

5th Annual IEEE International ASIC conference and Exhibit, ASIC 1992

作者： Kenney, T.J. D'Luna, L.J. Milch, J.R. Brown, G.W. Cook, W.A. Shafer, M.E. Berarducci, T.N. Eastman Kodak Co. RochesterNY14650-2036 United States

ISBN: (纸本)0780307682

A single chip that can perform three-channel 1∗4 serial color matrixing, 3∗4 color matrixing, 3∗3 (2-D) convolution, and a nine-TAP FIR filter has been designed in a 1- mu m gate array. The chip operates at 25 MHz and is useful for color optimization in scanning applications using linear CCD sensors, in electronic imaging applications using area sensors, and in a variety of image processing applications such as edge direction, enhancement, filtering and precompression processing. © 1992 IEEE.

关键词： Color

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2nd Joint International conference on Vector and parallel processing, CONPAR 1992

2nd Joint International Conference on Vector and Parallel Pr...

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2nd Joint International conference on Vector and parallel processing, CONPAR 1992

ISBN: (纸本)9783540558958

The proceedings contain 130 papers. The special focus in this conference is on Vector and parallel processing. The topics include: Tolerating faults in synchronization networks;on incomplete hypercubes;reducing network hardware quantity by employing multi-processor cluster structure in distributed memory parallel processors;connection machine results for pyramid embedding algorithms;interconnection networks based on block designs;partitioning and mapping communication graphs on a modular reconfigurable parallel architecture;generalized shuffle-exchange networks;a mechanism for integrating a visualization tool with a symbolic debugger;the software-monitor DELTA-T and its use for performance measurements of some farming variants on the multi-transputer system damp;visualization of message passing parallel programs;parallel physical optimization algorithms for data mapping;profiling on a massively parallel computer;a multiprocessor multiwindow visualization subsystem;data race detection based on execution replay for parallel applications;the C_NET programming environment: an overview;P++, a C++ virtual shared grids based programming environment for architecture-independent development of structured grid applications;detection of concurrency-related errors in joyce;invariance properties in distributed systems;synchronization of parallel processes in distributed systems;statistical probabilistic clock synchronization algorithm;a SIMD architecture for medical imaging;computing the inner product on reconfigurable buses with shift switching;a novel sorting array processor;the time-parallel solution of parabolic partial differential equations using the frequency-filtering method;comparing the DAP, meiko and suprenum with a fluid dynamic benchmark and parallel detection algorithm of radar signals.

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A serial/parallel color matrix, 2D convolution and 9-Tap filter ASIC with a systems perspective

A serial/parallel color matrix, 2D convolution and 9-Tap fil...

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Annual IEEE International conference and Exhibit ASIC

作者： T.J. Kenney L.J. D'Luna J.R. Milch G.W. Brown W.A. Cook M.E. Shafer T.N. Berarducci Eastman Kodak (Japan) Limited Rochester NY USA

A single chip that can perform three-channel 1*4 serial color matrixing, 3*4 color matrixing, 3*3 (2-D) convolution, and a nine-TAP FIR filter has been designed in a 1- mu m gate array. The chip operates at 25 MHz and is useful for color optimization in scanning applications using linear CCD sensors, in electronic imaging applications using area sensors, and in a variety of image processing applications such as edge direction, enhancement, filtering and precompression processing.< >

关键词： Convolution Application specific integrated circuits Finite impulse response filter Image processing Cost function Filtering Image color analysis Concurrent computing Charge coupled devices Table lookup

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A neural network calorimeter trigger used in CDF

A neural network calorimeter trigger used in CDF

引用

IEEE Symposium on Nuclear Science (NSS/MIC)

作者： W. Badgett K. Burkett M. Campbell D.Y. Wu B. Denby C. Lindsey R. Blair S. Kuhlmann J. Romano University of Michigan Ann Arbor MI USA FNAL Batavia IL USA ANL Argonne IL USA University of Chicago Chicago IL USA

The authors describe a pattern recognition electronic trigger, built around an INTEL 80170NX analog neural network chip, supported by 10 full FASTBUS cards and 48 signal tap boards. One of the applications takes advantage of the chip's parallel processing ability, using it as an analog arithmetic unit, to select isolated particles, based on 50 input signals. Preliminary performance results from data collected at the CDF (Collider Detector at Fermilab) high-energy physics experiment at Fermilab's proton-antiproton collider are shown.< >

关键词： Neural networks Intelligent networks Poles and towers Detectors Switches Hardware Content addressable storage Arithmetic Signal processing Time of arrival estimation

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Aladdin: a high performance, distributed memory multiprocessor

Aladdin: a high performance, distributed memory multiprocess...

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Annual Hawaii International conference on System Sciences (HICSS)

作者： M. Lum J. Brandt M. Vojta W. Wehner R. Belt Research and Technology Center Alliant Tech Systems Inc. Hopkins MN USA

Describes the design of the Aladdin architecture and the implementation of the prototype which Alliant Techsystems is under contract to deliver to DARPA and the Army's CCNVEO. The primary goal of the Aladdin project is to design an architecture that has high throughput and is compact, programmable, modular, reconfigurable and scalable. The architecture must be suitable for automatic target recognition (ATR) and radar processing, get flexible enough to be reconfigured for applications such as avionics processing. The architecture is demonstrated in a soupcan-sized prototype that consists of 64 320C30's with 92 MBytes of memory, and 16 Alliant Techsystems proprietary parallel Recirculating Pipeline (PREP) chips supported by 512 KBytes of multiport memory. It has a throughput of 2 GFLOPS, 1 GOPS, 1056 MIPS, and can be programmed in Ada, C and Image Algebra.< >

关键词： Throughput Prototypes Radar applications Scalability Integrated circuit interconnections Contracts Aerospace electronics Pipelines Algebra Radar imaging

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An 8-channel 16 b charge-to-digital converter for imaging applications

An 8-channel 16 b charge-to-digital converter for imaging ap...

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IEEE International conference on Solid-State Circuits (ISSCC)

作者： P. Holloway G. O'Donoghue Analog Devices Inc.orporated Wilmington MA USA Analog Devices Inc. Wilmington MA USA

An 8-channel 16-b charge-to-digital converter is described. Phothomic signals are inherently quantized and Poisson-noise limited. The diagram presented plots as binary exponents both the output code and the number of input electrons for signals converted by a multichannel, fully parallel floating-point CDAS (charge-input data acquisition system) chip containing 8 ADCs (analog-to-digital converters). These converters use the RipSaw algorithm, named for the circular-saw-blade shape of the characteristic voltage-conversion waveform. The analog signal processor for each pipelined conversion channel is shown. Bandlimited integrators combined with dual, noise-shaping SHAs allow each channel to achieve a 55-kHz NEB (noise effective bandwidth) at 20 kS/s. The analog signal processor is combined with the RipSaw mantissa, exponent, and control logic to complete one CDAS channel. Each of the twelve switches in every CDAS is charge-compensated with slew rate and differential delay adjusted to optimized charge injection and/or partition noise.< >

关键词： Signal processing Noise shaping Electrons Data acquisition Analog-digital conversion Signal processing algorithms Shape Voltage Bandwidth Logic

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A HIGH-PERFORMANCE parallel COMPUTING SYSTEM FOR imaging AND GRAPHICS

A HIGH-PERFORMANCE PARALLEL COMPUTING SYSTEM FOR IMAGING AND...

引用

IEEE PACIFIC RIM CONF ON COMMUNICATIONS COMPUTER AND SIGNAL processing

作者： PARK, HW ALEXANDER, T MOON, SH KIM, Y

ISBN: (纸本)0879426381

UWGSP4 (University of Washington Graphics System Processor) consists of four parts: a parallel vector processor, a shared-memory system, an interconnection network, and a graphics subsystem. The parallel vector processor was provided mainly for imaging and general-purpose computing, whereas the main functions of the graphics subsystem are to generate realistic three-dimensional images and to draw the display screen. Among the four parts, the shared memory and the interconnection network were designed to fully support the parallel vector processor and graphics subsystem so as to yield high sustained performance. A discussion is presented of the architecture of UWGSP4, simulated performance figures for several imaging and graphics algorithms, and applications areas.

关键词： Computer Systems, Digital

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INTERFACING A RADIOLOGY INFORMATION-SYSTEM AND A PICTURE ARCHIVING AND COMMUNICATION-SYSTEM

INTERFACING A RADIOLOGY INFORMATION-SYSTEM AND A PICTURE ARC...

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IEEE PACIFIC RIM CONF ON COMMUNICATIONS COMPUTER AND SIGNAL processing

作者： SOEHLKE, K ATKINSON, J FISHER, P Sch of Health Inf Sci Univ of Victoria BC Canada

ISBN: (纸本)0879426381

In some medical imaging (MI) departments two information systems have developed in parallel, a radiology information management system (RIMS) and a picture archiving and communication system (PACS). A connection between the two applications is required to adequately support the medical imaging process and is vital to a completely digital MI department. The RIMS-PACS interface will provide the mechanism for single-point access to all of the information required by a radiologist for a diagnosis. The authors describe the results of the analysis of the two systems and outline possibilities for their interconnection. The high-level design of the RIMS-PACS interface as reported will satisfy the clinical users' need for single-point access to the data required for clinical radiology. It overcomes the obstacles presented by the low connectivity of the two applications. The complexity of the analysis required to design the interface highlights the need for more strategic planning before information systems are implemented.

关键词： Image processing

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A new concurrent processing system for medical stereo radiographs

A new concurrent processing system for medical stereo radiog...

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Proceedings of the 1991 International conference on Industrial Electronics, Control and Instrumentation - IECON '91

作者： Wang, Qing-yuan Zheng, Nan-ning Liu, Jian-qin Li, Jian-wu

A new stereo processing system for medical X-ray imaging, based on the principle of stereo imaging and display, is presented. The whole system consists of three subsystems: (1) the X-ray control unit, (2) the image acquisition and processing subsystem, and (3) the stereo display subsystem. The parallel structure with two channels for X-ray image processing, the digital substraction angiography technique, and the stereo depth determination technique with the interaction mode are described. The architecture of the system and the improved reconstructed stereographic X-ray image display system are introduced. The merits of the system and applications are discussed.

关键词： X ray radiography

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