The authors describe a pattern recognition electronic trigger, built around an INTEL 80170NX analog neural network chip, supported by 10 full FASTBUS cards and 48 signal tap boards. One of the applications takes advan...
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The authors describe a pattern recognition electronic trigger, built around an INTEL 80170NX analog neural network chip, supported by 10 full FASTBUS cards and 48 signal tap boards. One of the applications takes advantage of the chip's parallelprocessing ability, using it as an analog arithmetic unit, to select isolated particles, based on 50 input signals. Preliminary performance results from data collected at the CDF (Collider Detector at Fermilab) high-energy physics experiment at Fermilab's proton-antiproton collider are shown.< >
Describes the design of the Aladdin architecture and the implementation of the prototype which Alliant Techsystems is under contract to deliver to DARPA and the Army's CCNVEO. The primary goal of the Aladdin proje...
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Describes the design of the Aladdin architecture and the implementation of the prototype which Alliant Techsystems is under contract to deliver to DARPA and the Army's CCNVEO. The primary goal of the Aladdin project is to design an architecture that has high throughput and is compact, programmable, modular, reconfigurable and scalable. The architecture must be suitable for automatic target recognition (ATR) and radar processing, get flexible enough to be reconfigured for applications such as avionics processing. The architecture is demonstrated in a soupcan-sized prototype that consists of 64 320C30's with 92 MBytes of memory, and 16 Alliant Techsystems proprietary parallel Recirculating Pipeline (PREP) chips supported by 512 KBytes of multiport memory. It has a throughput of 2 GFLOPS, 1 GOPS, 1056 MIPS, and can be programmed in Ada, C and Image Algebra.< >
An 8-channel 16-b charge-to-digital converter is described. Phothomic signals are inherently quantized and Poisson-noise limited. The diagram presented plots as binary exponents both the output code and the number of ...
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An 8-channel 16-b charge-to-digital converter is described. Phothomic signals are inherently quantized and Poisson-noise limited. The diagram presented plots as binary exponents both the output code and the number of input electrons for signals converted by a multichannel, fully parallel floating-point CDAS (charge-input data acquisition system) chip containing 8 ADCs (analog-to-digital converters). These converters use the RipSaw algorithm, named for the circular-saw-blade shape of the characteristic voltage-conversion waveform. The analog signal processor for each pipelined conversion channel is shown. Bandlimited integrators combined with dual, noise-shaping SHAs allow each channel to achieve a 55-kHz NEB (noise effective bandwidth) at 20 kS/s. The analog signal processor is combined with the RipSaw mantissa, exponent, and control logic to complete one CDAS channel. Each of the twelve switches in every CDAS is charge-compensated with slew rate and differential delay adjusted to optimized charge injection and/or partition noise.< >
UWGSP4 (University of Washington Graphics System Processor) consists of four parts: a parallel vector processor, a shared-memory system, an interconnection network, and a graphics subsystem. The parallel vector proces...
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ISBN:
(纸本)0879426381
UWGSP4 (University of Washington Graphics System Processor) consists of four parts: a parallel vector processor, a shared-memory system, an interconnection network, and a graphics subsystem. The parallel vector processor was provided mainly for imaging and general-purpose computing, whereas the main functions of the graphics subsystem are to generate realistic three-dimensional images and to draw the display screen. Among the four parts, the shared memory and the interconnection network were designed to fully support the parallel vector processor and graphics subsystem so as to yield high sustained performance. A discussion is presented of the architecture of UWGSP4, simulated performance figures for several imaging and graphics algorithms, and applications areas.
In some medical imaging (MI) departments two information systems have developed in parallel, a radiology information management system (RIMS) and a picture archiving and communication system (PACS). A connection betwe...
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ISBN:
(纸本)0879426381
In some medical imaging (MI) departments two information systems have developed in parallel, a radiology information management system (RIMS) and a picture archiving and communication system (PACS). A connection between the two applications is required to adequately support the medical imaging process and is vital to a completely digital MI department. The RIMS-PACS interface will provide the mechanism for single-point access to all of the information required by a radiologist for a diagnosis. The authors describe the results of the analysis of the two systems and outline possibilities for their interconnection. The high-level design of the RIMS-PACS interface as reported will satisfy the clinical users' need for single-point access to the data required for clinical radiology. It overcomes the obstacles presented by the low connectivity of the two applications. The complexity of the analysis required to design the interface highlights the need for more strategic planning before information systems are implemented.
A new stereo processing system for medical X-ray imaging, based on the principle of stereo imaging and display, is presented. The whole system consists of three subsystems: (1) the X-ray control unit, (2) the image ac...
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A new stereo processing system for medical X-ray imaging, based on the principle of stereo imaging and display, is presented. The whole system consists of three subsystems: (1) the X-ray control unit, (2) the image acquisition and processing subsystem, and (3) the stereo display subsystem. The parallel structure with two channels for X-ray image processing, the digital substraction angiography technique, and the stereo depth determination technique with the interaction mode are described. The architecture of the system and the improved reconstructed stereographic X-ray image display system are introduced. The merits of the system and applications are discussed.
UWGSP4 (University of Washington Graphics System Processor) consists of four parts: a parallel vector processor, a shared-memory system, an interconnection network, and a graphics subsystem. The parallel vector proces...
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UWGSP4 (University of Washington Graphics System Processor) consists of four parts: a parallel vector processor, a shared-memory system, an interconnection network, and a graphics subsystem. The parallel vector processor was provided mainly for imaging and general-purpose computing, whereas the main functions of the graphics subsystem are to generate realistic three-dimensional images and to draw the display screen. Among the four parts, the shared memory and the interconnection network were designed to fully support the parallel vector processor and graphics subsystem so as to yield high sustained performance. A discussion is presented of the architecture of UWGSP4, simulated performance figures for several imaging and graphics algorithms, and applications areas.< >
A stereo processing system for medical X-ray imaging, based on the principle of stereo imaging and display, is presented. The whole system consists of three subsystems: the X-ray control unit, the image acquisition an...
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A stereo processing system for medical X-ray imaging, based on the principle of stereo imaging and display, is presented. The whole system consists of three subsystems: the X-ray control unit, the image acquisition and processing subsystem, and the stereo display subsystem. The parallel structure with two channels for X-ray image processing, the digital subtraction angiography technique, and the stereo depth determination technique with the interaction mode are described. The architecture of the system and the improved reconstructed stereographic X-ray image display system are introduced. The merits of the system and applications are discussed.< >
Neural network technology has reached the stage where practical applications are appearing. However, the computational resources required to perform the data manipulation are large and complex. Hardware to perform neu...
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Neural network technology has reached the stage where practical applications are appearing. However, the computational resources required to perform the data manipulation are large and complex. Hardware to perform neural network computations has been slow to appear. The causes for these limitations are reviewed, along with the state-of-the-art in neural network hardware. Novel methods to circumvent these limitations are suggested: hybrid optical/electronic systems neural network algorithms specifically formatted to match to digital semiconductor chips; fine grained parallel simulators using a novel neuron value transfer; and massive analog semiconductor chips.< >
This conference proceedings contains 25 papers. The main subjects are color image processing, median and order statistic filters, morphological and stack filters, nonlinear filters, neural networks applications, image...
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ISBN:
(纸本)081940294X
This conference proceedings contains 25 papers. The main subjects are color image processing, median and order statistic filters, morphological and stack filters, nonlinear filters, neural networks applications, image-processing algorithms, and image recognition and learning in parallel networks.
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