In this paper, we present a new method for quantifying color information so as to detect edges in color images. Our method uses the volume of a pixel in the HSI color space, allied with noise reduction, thresholding a...
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ISBN:
(纸本)9780889869073
In this paper, we present a new method for quantifying color information so as to detect edges in color images. Our method uses the volume of a pixel in the HSI color space, allied with noise reduction, thresholding and edge thinning. We implement our algorithm using NVIDIA Compute Unified Device Architecture (CUDA) for direct execution on Graphics processing Units (GPUs). Our experimental results show that: compared to traditional edge detection methods, our method can improve the accuracy of edge detection and withstand greater levels of noise in images;and our GPU implementation achieves speedups over related CUDA implementations.
Band selection is a common technique for dimensionality reduction of hyperspectral imagery. When the desired object information is unknown, an unsupervised band selection approach is employed to select the most distin...
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ISBN:
(纸本)9780769545769
Band selection is a common technique for dimensionality reduction of hyperspectral imagery. When the desired object information is unknown, an unsupervised band selection approach is employed to select the most distinctive and informative bands. However, it may be time-consuming for unsupervised band selection methods that need to take all pixels into consideration. Here, we propose an approach to select several pixels for unsupervised band selection and the number of pixels required can be equal to the number of bands to be selected minus 1. With whitened pixel signatures (not the original pixels), band selection performance can be comparable to or even better than that from using all the pixels. For this approach, graphics processing unit (GPU)-based parallel computing is implemented for pixel selection only to further expedite the process, since computational complexity in band selection has been greatly reduced.
A low power vision system has been developed incorporating the SCAMP3 pixel-parallel processor array vision chip. A test algorithm to detect loitering targets has shown an average power consumption of <6mW analysin...
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ISBN:
(纸本)9781457717079
A low power vision system has been developed incorporating the SCAMP3 pixel-parallel processor array vision chip. A test algorithm to detect loitering targets has shown an average power consumption of <6mW analysing 128x128 images at 8 frames per second.
For constructing the support set of a sparse vector in the standard compressive sensing framework, we develop a hybrid greedy pursuit algorithm that combines the advantages of serial and parallel atom selection strate...
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For constructing the support set of a sparse vector in the standard compressive sensing framework, we develop a hybrid greedy pursuit algorithm that combines the advantages of serial and parallel atom selection strategies. In an iterative framework, the hybrid algorithm uses a joint sparsity information extracted from the independent use of serial and parallel greedy pursuit algorithms. Through experimental evaluations, the hybrid algorithm is shown to provide a significant improvement for the support set recovery performance.
Increasingly complex systems need parallelized simulation engines. In the context of SystemC simulation, existing proposals require predicting communication in the simulated system. However, this is often unpredictabl...
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Real-time H.264 encoding of high-definition (HD) video (up to 1080p) is a challenge workload to most existing programmable processors. Instead, the novel programmable parallel processors such as stream processor, Grap...
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The research was carried out to build a patient management system and decision support system (considering certain types of Leukaemia as the domain) for the Hematology Department of Hospital Kuala Lumpur (HKL), Malays...
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Video compression algorithms such as H.264 offer much potential for parallelprocessing that is not always exploited by the technology of a particular implementation. Consumer mobile encoding devices often achieve rea...
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ISBN:
(纸本)9780819486370
Video compression algorithms such as H.264 offer much potential for parallelprocessing that is not always exploited by the technology of a particular implementation. Consumer mobile encoding devices often achieve real-time performance and low power consumption through parallelprocessing in Application Specific Integrated Circuit (ASIC) technology, but many other applications require a software-defined encoder. High quality compression features needed for some applications such as 10-bit sample depth or 4:2:2 chroma format often go beyond the capability of a typical consumer electronics device. An application may also need to efficiently combine compression with other functions such as noise reduction, image stabilization, real time clocks, GPS data, mission/ESD/user data or software-defined radio in a low power, field upgradable implementation. Low power, software-defined encoders may be implemented using a massively parallel memory-network processor array with 100 or more cores and distributed memory. The large number of processor elements allow the silicon device to operate more efficiently than conventional DSP or CPU technology. A dataflow programming methodology may be used to express all of the encoding processes including motion compensation, transform and quantization, and entropy coding. This is a declarative programming model in which the parallelism of the compression algorithm is expressed as a hierarchical graph of tasks with message communication. Data parallel and task parallel design patterns are supported without the need for explicit global synchronization control. An example is described of an H.264 encoder developed for a commercially available, massively parallel memory-network processor device.
According to the uniform addressing and direct localization of network address space, adopting multi-threaded, multi-copy store and block storage in pages, page tree sub-node parallel failure methods, these can improv...
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According to the uniform addressing and direct localization of network address space, adopting multi-threaded, multi-copy store and block storage in pages, page tree sub-node parallel failure methods, these can improve the efficiency and parallelprocessing of the DSM system. It is significance for improving the performance of distributed systems. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of [CEIS 2011]
The proceedings contain 68 papers. The topics discussed include: trusted computing dynamic attestation by using static analysis based behavior model;evolutionary design of S-box with cryptographic properties;a multi-l...
ISBN:
(纸本)9780769544298
The proceedings contain 68 papers. The topics discussed include: trusted computing dynamic attestation by using static analysis based behavior model;evolutionary design of S-box with cryptographic properties;a multi-level grey evaluation model for harms of computer virus;reduce leakage currents in low power SRAM cell structures;concurrent online test architecture for multiple controller blocks with minimum fault latency;modeling and analysis of radiation therapy system with respiratory compensation using uppaal;brushstroke control from image saliency;tomogrphical medical image reconstruction using kalman filter technique;affordable privacy for home smart meters;scheduling of energy storage systems with geographically distributed renewables;selection of model in developing information security criteria on smart grid security system;and two-layer security scheme for AMI system in Taiwan.
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