The proceedings contain 78 papers. The topics discussed include: offset compensation for differential charge-based capacitance measurement;sub-100 ps modular asynchronous readout for single event cluster detection in ...
ISBN:
(纸本)9798350386301
The proceedings contain 78 papers. The topics discussed include: offset compensation for differential charge-based capacitance measurement;sub-100 ps modular asynchronous readout for single event cluster detection in pixel sensor applications;analysis anddesign of high-speed, linear and fullscale input swing voltage to time converters;computationally efficient RF band and base band beam-former for coherent plane wave imaging;a reconfigurable high-efficiency all-PMOS charge pump with dual-phase clock scheme;a 10-MHz three-level buck converter with dual-loop time-based control and flying capacitor voltage-balance for fast dVS;empowering smart mobility with a component-baseddata acquisition system for multi-sensor readout;and a 4T GC-edRAM Bitcell with differential readout mechanism for high performance applications.
The proceedings contain 95 papers. The topics discussed include: switching mode power amplifier for fully digital RF transmitter at 3.6 GHz in 22 nm Fd-SOI CMOS;improving performance of InGaP/GaAs HBT arrays by means ...
ISBN:
(纸本)9798350303209
The proceedings contain 95 papers. The topics discussed include: switching mode power amplifier for fully digital RF transmitter at 3.6 GHz in 22 nm Fd-SOI CMOS;improving performance of InGaP/GaAs HBT arrays by means of temperature-dependent base ballasting resistors;a novel ultra-low voltage fully synthesizable comparator exploiting NANd gates;robust body biasing techniques for dynamic comparators;analysis anddesign of a low power double tail comparator with dynamic bias in 5nm FinFET technology;minimizing quiescent power in a dynamically biased comparator and its application in relaxation oscillator;an asynchronous constant TOFF, 10 A, buck converter with peak current mode control for automotive applications;control circuits for adjustable digitally programmeddC power supplies;a novel high-performance parallel-type slew-rate enhancer for LCd-driving applications;and a scalable frame-based readout architecture for monolithic pixel detectors with local AdC and time digitization.
The proceedings contain 94 papers. The topics discussed include: immunity of ENOP-based fractional-n frequency synthesizer to wandering and horn spurs;a configurable active bandpass filter with dc offset suppression f...
ISBN:
(纸本)9781665467001
The proceedings contain 94 papers. The topics discussed include: immunity of ENOP-based fractional-n frequency synthesizer to wandering and horn spurs;a configurable active bandpass filter with dc offset suppression for direct down-conversion wake-up receivers in 28 nm;a distributed amplitude control loop for VCO-array-based EPR-on-a-chip detectors;defect detection in double-sided cooled power modules by structure functions;manufacturing of silver-ink micrometer inductors through multilayer d.O.d. printing for vhf power transfer;using formal methods to evaluate hardware reliability in the presence of soft errors;three-wavelength SPAd-basedphotoplethysmography;planar capacitive transducers for a miniaturized particulate matter detector;quantum dots for explosive detection in air - two complimentary approaches;and interface circuit for low-resistance sensors based on noise cancelling technique.
The proceedings contain 5 papers. The topics discussed include: low-power activity recognition from triaxial accelerometer data;a compact functional verification flow for a RISC-V 32I based core;pre-synthesis evaluati...
ISBN:
(纸本)9781728131467
The proceedings contain 5 papers. The topics discussed include: low-power activity recognition from triaxial accelerometer data;a compact functional verification flow for a RISC-V 32I based core;pre-synthesis evaluation of digital bus micro-architectures;ultra-low power relaxation oscillators survey: design trends and challenges;and PlasticNet: a low latency flexible network architecture for interconnected multi-FPGA systems.
Implantable medical devices present several implementation challenges. In the development of neural prosthetic systems, specifically in the field of modular systems, a significant aspect is the transmission of power f...
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ISBN:
(纸本)9798350386301;9798350386318
Implantable medical devices present several implementation challenges. In the development of neural prosthetic systems, specifically in the field of modular systems, a significant aspect is the transmission of power from the main unit to the neural stimulation and recording modules distributed along the body, together with bidirectional communication between the units. In this regard, a demodulation circuit for wired power transmission and bidirectional communication between implanted chips, implemented in 180nm CMOS technology is proposed.
The proceedings contain 77 papers. The topics discussed include: self-synchronized encryption using an FPE block cipher for gigabit Ethernet;performance parameters modeling and simulation of single-photon avalanche di...
ISBN:
(纸本)9781728135496
The proceedings contain 77 papers. The topics discussed include: self-synchronized encryption using an FPE block cipher for gigabit Ethernet;performance parameters modeling and simulation of single-photon avalanche diodes for space lidar applications;modeling of implantable photovoltaic cells based on human skin types;minimum energy point in constant frequency designs under adaptive supply voltage and body bias adjustment in 55 nm ddC;startup behavior of power management unit for an integrated gate driver;implementation of a fully-differential operational amplifier with wide-input range, high-impedance common-mode feedback;a high performance full-word Barrett multiplier designed for FPGAs with dSP resources;and effect of SSN on signal and power integrity on 32-bit microcontroller : modeling and correlation.
Neurostimulation applications require increasing versatility to tailor the treatment to the patient needs, thus improving its efficacy. In this work, we propose a fully-programmable integrated neurostimulation system ...
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ISBN:
(纸本)9798350386301;9798350386318
Neurostimulation applications require increasing versatility to tailor the treatment to the patient needs, thus improving its efficacy. In this work, we propose a fully-programmable integrated neurostimulation system capable of performing biphasic stimulation with a maximum stimuli current of +/- 10 mA, a maximum frequency stimulation of 50 kHz and a reduced charge mismatch of only 0.07%. Accurate electrical simulations were performed on a prototype designed with 180nm standard CMOS process, validating the effectiveness of the proposed circuit. The obtained results are comparable with the state of the art.
Memristive crossbar arrays enable fast and efficient implementation of analog vector-matrix multiplication as hardware accelerators for computational neural networks. The individual analog building blocks for precise ...
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ISBN:
(纸本)9798350386301;9798350386318
Memristive crossbar arrays enable fast and efficient implementation of analog vector-matrix multiplication as hardware accelerators for computational neural networks. The individual analog building blocks for precise and reliable operation play a key role for the resulting performance. This paper presents a voltage buffer with high speed current sensing for fast read-out of the multiplication results. An operational amplifier with two current matching outputs is proposed as viable alternative to classic TIA baseddesigns.
This paper presents a digital OTA topology with a modified input stage, leveraging a complementary Muller stage and Muller- based current mirrors to increase the linearity. By employing a 180-nm standard CMOS technolo...
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ISBN:
(纸本)9798350386301;9798350386318
This paper presents a digital OTA topology with a modified input stage, leveraging a complementary Muller stage and Muller- based current mirrors to increase the linearity. By employing a 180-nm standard CMOS technology and operating with a supply voltage down to 0.3 V, simulations demonstrate a 54.5-dB gain and a 265 Hz gain bandwidth product when driving a 150-pF capacitive load. In comparison to other ultra-low-voltage OTAs reported so far in the literature, the proposed work leads to an enhancement in signal linearity (total harmonic distortion is 0.7% at 0.3V and 0.3% at 0.5V) and in the common mode and power-supply rejection ratios, to respectively 93dB and 63.9dB.
Comparators are vital building blocks for integrated power electronics. Monolithic integration of switches anddrivers in high-voltage GaN processes have shown significant performance benefits, while analog circuits s...
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ISBN:
(纸本)9798350386301;9798350386318
Comparators are vital building blocks for integrated power electronics. Monolithic integration of switches anddrivers in high-voltage GaN processes have shown significant performance benefits, while analog circuits still fall behinddue to offset and noise. An auto-zero comparator design optimized for propagation delay, noise and offset voltage is proposed. It employs multiple AC-coupled gain stages, which are zeroed sequentially to reduce input referred offset and low-frequency noise. Simulations of the proposed comparator are performed using noise and mismatch models extracted from a physical reference design and manufactured test structures. The proposeddesign achieves 81 dB of gain with 9.3 ns propagation delay. Monte Carlo and noise simulations yield a 1-sigma offset of 1.2mV and 18.2 mu V-rms integral input noise.
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