检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

811 篇 会议
25 篇 期刊文献

馆藏范围

836 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

509 篇 工学
- 327 篇 电气工程
- 213 篇 电子科学与技术（可...
- 101 篇 计算机科学与技术...
- 64 篇 信息与通信工程
- 46 篇 软件工程
- 26 篇 控制科学与工程
- 25 篇 材料科学与工程（可...
- 20 篇 动力工程及工程热...
- 17 篇 生物医学工程（可授...
- 16 篇 化学工程与技术
- 14 篇 仪器科学与技术
- 12 篇 机械工程
- 12 篇 光学工程
- 9 篇 生物工程
- 7 篇 航空宇航科学与技...
- 5 篇 力学（可授工学、理...
- 5 篇 冶金工程
- 5 篇 建筑学
- 5 篇 安全科学与工程
115 篇 理学
- 66 篇 物理学
- 47 篇 数学
- 15 篇 化学
- 9 篇 生物学
- 8 篇 统计学（可授理学、...
- 6 篇 系统科学
19 篇 管理学
- 19 篇 管理科学与工程(可...
6 篇 法学
- 6 篇 社会学
6 篇 医学
- 6 篇 临床医学
- 5 篇 基础医学(可授医学...
- 5 篇 药学(可授医学、理...
2 篇 经济学
1 篇 教育学
1 篇 农学

主题

43 篇 cmos integrated ...
41 篇 microelectronics
33 篇 transistors
30 篇 switches
28 篇 power demand
25 篇 logic gates
25 篇 clocks
25 篇 capacitors
24 篇 topology
23 篇 noise
23 篇 integrated circu...
22 篇 bandwidth
21 篇 gain
21 篇 capacitance
20 篇 silicon
20 篇 cmos technology
19 篇 simulation
19 篇 mathematical mod...
18 篇 computer archite...
18 篇 modulation

机构

21 篇 tech univ dresde...
13 篇 department of el...
12 篇 institute of mic...
7 篇 fondazione bruno...
7 篇 univ salento dep...
6 篇 rhein westfal th...
6 篇 institute of ele...
6 篇 fraunhofer inst ...
6 篇 univ milano bico...
5 篇 robert bosch cen...
5 篇 stmicroelectroni...
5 篇 politecn milan d...
4 篇 univ federico ii...
4 篇 univ ulm inst mi...
4 篇 melexis gmbh erf...
4 篇 univ milano bico...
4 篇 univ pavia dept ...
4 篇 department of ph...
4 篇 institute of mic...
4 篇 kai villach aust...

作者

29 篇 ellinger frank
29 篇 heinen stefan
19 篇 wunderlich ralf
15 篇 joram niko
13 篇 baschirotto a.
12 篇 maurits ortmanns
11 篇 catherine deholl...
11 篇 de matteis m.
10 篇 franco maloberti
10 篇 baschirotto andr...
10 篇 d'amico s.
9 篇 ortmanns maurits
9 篇 berroth manfred
8 篇 maloberti franco
8 篇 kokozinski raine...
8 篇 negra renato
7 篇 groezing markus
7 篇 yusuf leblebici
7 篇 el-shennawy moha...
7 篇 d'amico stefano

语言

813 篇 英文
13 篇 中文
10 篇 其他

检索条件"任意字段=Conference on Ph.D Research in Microelectronics and Electronics"

共 836 条记录，以下是101-110 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Low-complexity Machine Learning Architecture for Hardware-aware True Random Number Generators Assessment and Continuous Monitoring

Low-complexity Machine Learning Architecture for Hardware-aw...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： F. Spinelli R. Moretti T. Addabbo P. Vitolo G. d. Licciardo Dept. of Information Engineering and Mathematics University of Siena Siena Italy Dept. of Industrial Engineering University of Salerno Fisciano SA Italy

A new machine learning approach of assessment and monitoring of True Random Number Generators (TRNGs) is explored in order to create a new technical framework for entropy source development and validation, based on the direct estimation of the core source entropy, which is suitable for hardware-based lightweight cryptography. It consists of the integration between a pre-processing stage and an Artificial Neural Network (ANN). The pre-processing stage continuously generates stochastically patterned images from number sequences provided by TRNGs with assigned entropy thresholds. The ANN processes the images to determine whether the TRNG entropy remains higher than the assigned threshold, dynamically, during the sequence generation. A custom dataset, generated from a Markovian TRNG has been used to train, validate and test a very compact 3-layer ANN. The model achieves accuracy, precision, recall, and F-score all equal to 98.28% averaged on the test set. The low computational complexity of the ANN, favored by the effectiveness of the pre-processing stage, which, in turn, requires a simple architecture to be implemented, proves that the proposed solution can be effectively employed for a perspective resource-constrained hardware implementation.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Mismatch Based Implementation of W Band LNA Using GaAs phEMTs

Mismatch Based Implementation of W Band LNA Using GaAs pHEMT...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： Shikha Swaroop Sharma Swati Sharma Pattrick Longhi Sergio Colangeli Walter Ciccognani Ernesto Limiti Department of Electronics Engineering University of Rome Tor Vergata Rome Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

Ultra-low noise W Band amplifier has been implemented using 0.1um GaAs phEMT technology. Four stages common source degeneration topology has been used to achieve less noise figure and stability. The bias network is designed to ensure stability from dC to 120 GHz. The LNA possesses the results after measurement showed the small signal gain of 19dB from 92-115 GHz with the noise figure less than 4.6dB. The fabricated LNA shows the highest operative bandwidth among those for which measured data are available in the relevant literature. The fabricated prototype occupies an active chip area of 4 × 2.5mm 2 with power consumption constraint at 80mW from the 2V supply voltage.

关键词： Noise figure Semiconductor device measurement Power demand phEMTs Gallium arsenide Noise Bandwidth

来源：评论

学校读者我要写书评

暂无评论

A Reconfigurable High-Efficiency All-PMOS Charge Pump with dual-phase Clock Scheme

A Reconfigurable High-Efficiency All-PMOS Charge Pump with D...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： Xingyuan Chen Berkay Özbek Peilong Feng Timothy Constandinou Department of Electrical and Electronic Engineering Imperial College London UK Care Research & Technology Centre Imperial College London UK Dementia Research Institute Mint Neurotechnologies Ltd London UK

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

This paper presents a reconfigurable high-efficiency charge pump design in 180nm CMOS technology. This charge pump is designed for high-voltage and low-power applications including programmable anti-fuse memory and powering wireless neural interfaces. It generates a variable voltage of up to 10.73V from a 1.8V supply voltage. It employs a novel dual-phase overlapping clock control scheme to minimise losses during clock transitions. The proposed clocks are generated by a full-custom clock generator with a single clock input. Simulation results demonstrate the charge pump achieves a peak power conversion efficiency (PCE) of 94.65% at an output current of 200µA. By enabling the pumping clocks of the corresponding stages, the stage number is adjustable and the output voltage can be changed between 0 and 10.73V. With the proposed novel clock scheme and programmable stage number, the optimum PCE is obtained within a wide range of output currents and voltages.

关键词： Wireless communication Charge pumps Simulation Logic gates Generators Topology microelectronics

来源：评论

学校读者我要写书评

暂无评论

Efficient Saturation Control for Fully differential Integrator in Continuous-Time Sigma-delta Modulators

Efficient Saturation Control for Fully Differential Integrat...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： Matteo de Ferrari Francesco Stilgenbauer Edoardo Botti Cristiano Meroni Paolo Crovetti Edoardo Bonizzoni Piero Malcovati Dept. of Electrical Computer and Biomedical Engineering University of Pavia Pavia Italy STMicroelectronics Cornaredo MI Italy Dept. of Electronics and Telecommunications Politecnico di Torino Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

This paper presents an alternative approach to saturation control in an integrator, that occurs in Sigma-delta modulators (ΣΔMs). This solution simplifies the design process with a 1.2- V power supply and consumes significantly less power than conventional saturation control methods. Additionally, this solution provides a good phase margin, that guarantees the stability, without requiring additional compensation techniques, and it has the added benefit of reducing the gain of the integrator as the system enters saturation, while also maintaining integrator inputs fixed at the proper common-mode voltage. This innovative approach offers a promising solution for efficient and stable saturation control in ΣΔM integrators, preventing distortion in the output signal, with potential applications in a wide range of electronic systems, such as audio systems. The circuit has been designed in a 90-nm CMOS technology.

关键词： Operational amplifiers Sigma-delta modulation Transient response Power demand Audio systems Modulation Process control

来源：评论

学校读者我要写书评

暂无评论

design-Space Exploration of Mixed-precision dNN Accelerators based on Sum-Together Multipliers

Design-Space Exploration of Mixed-precision DNN Accelerators...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： Luca Urbinati Mario R. Casu Dept. Electronics and Telecommunications Politecnico di Torino Turin Italy

Mixed-precision quantization (MPQ) is gaining momentum in academia and industry as a way to improve the trade-off between accuracy and latency of deep Neural Networks (dNNs) in edge applications. MPQ requires dedicated hardware to support different bit-widths. One approach uses Precision-Scalable MAC units (PSMACs) based on multipliers operating in Sum-Together (ST) mode. These can be configured to compute N = 1, 2, 4 multiplications/dot-products in parallel with operands at 16/N bits. We contribute to the State of the Art (SoA) in three directions: we compare for the first time the SoA ST multipliers architectures in performance, power and area; compared to previous work, we contribute to the portfolio of ST-based accelerators proposing three designs for the most common dNN algorithms: 2d-Convolution, depth-wise Convolution and Fully-Connected; we show how these accelerators can be obtained with a High-Level Synthesis (HLS) flow. In particular, we perform a design-space exploration (dSE) in area, latency, power, varying many knobs, including PSMAC units parallelism, clock frequency and ST multipliers type. From the dSE on a 28-nm technology we observe that both at multiplier level and at accelerator level there is no one-fits-all solution for each possible scenario. Our findings allow accelerators’ designers to choose, out of a rich variety, the best combination of ST multiplier and HLS knobs depending on the target, either high performance, low area, or low power.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Computationally Efficient RF Band and Base band Beam-former for Coherent Plane Wave Imaging

Computationally Efficient RF Band and Base band Beam-former ...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： Zahraa Alzein Marco Crocco daniele d. Caviglia DITEN Department University of Genoa Genova Italy Esaote S.p.A. Genova Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

This study presents computationally efficient implementations of radio frequency (RF) band and baseband receive beamforming and coherent compounding applied to multi-angle plane wave transmission. The impact of the sampling frequency on image quality has been measured by standard metrics on simulated data for both approaches. Moreover, the computational cost in terms of processing time and floating point operations has been evaluated. Finally, the memory and transfer bandwidth requirements have been estimated for both focalization data and acquired raw data. The results demonstrate that baseband beam-forming can achieve acceptable image quality with a sampling frequency reduced roughly by a factor of 4 with respect to RF band beamforming. The consequent 4-fold reduction of required transfer bandwidth and memory storage for raw data comes at the cost of a mild increase in computational load of about 50%.

关键词： Radio frequency Image quality Baseband Array signal processing Memory management Imaging Bandwidth

来源：评论

学校读者我要写书评

暂无评论

Low-Power VCII-Based Current-Mode Schmitt Trigger with High drive Capabilities

Low-Power VCII-Based Current-Mode Schmitt Trigger with High ...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： davide Colaiuda Gianluca Barile Alfiero Leoni Vincenzo Stornelli Giuseppe Ferri DIIIE University of L 'Aquila L'Aquila Italy DEI Politecnico di Bari Bari Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

In this paper, a novel CMOS current-mode Schmitt Trigger based on the Second Generation Voltage Conveyor (VCII) is proposed. The circuit has been designed in a standard CMOS 150 nm technology with a dual ±1.65 V voltage supply, and simulations and layout were carried out on Cadence Virtuoso. Low power consumption is obtained using a class AB current input stage and a class B voltage push-pull output stage, providing two voltage outputs to better suit the load of the trigger. Static and transient simulations, as well as PVT and Montecarlo analyses, were performed. The designed VCII shows an output saturation value of approximately ±1.18 V on the high-drive output, used to generate the threshold, a mismatch of about 10mV between positive and negative values, and a rail-to-rail output. The static power consumption is 37 µW, and the high-drive capability overcomes ±98 V /µs and 100 ns propagation delay, making the proposed circuit suitable to be used as a Schmitt Trigger.

关键词： Semiconductor device modeling Low voltage Power demand Simulation microelectronics Transient analysis Tuning

来源：评论

学校读者我要写书评

暂无评论

design and Modellization of a Neural Network Used to Optimize and to Monitor a dC-dC Converter

Design and Modellization of a Neural Network Used to Optimiz...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： Sandeep Krishnan Nandialath Radhakrishnan Stefano Passi Alessandro Cabrini Francesco d'Angelo Alessandro Nicolosi Luca Iannelli Department of industrial and information engineering Università di Pavia-STMicroelectronics Pavia (PV) Italy Smart Power R&D STMicroelectronics Agrate (MB) Italy Department of industrial and information engineering Università di Pavia Pavia (PV) Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

The purpose of this paper is to describe the model and the design of a neural network (NN) that optimizes a dC-dC converter power management system. The dC-dC converter plays a crucial role in maintaining the output voltage within the desired range. However, the conventional power management system has limitations in handling nonlinearities and uncertainties in the system. The proposed approach exploits the capability of a NN to accurately estimate certain parameters of the circuit that are closely associated with the functionality of the feedback control loop. In the case under analysis, we use Proportional-Integral-derivative (PId) control to regulate the output voltage. Precise estimation of the real value of analog components involved in the computation of PId parameters can improve the control loop and overall performance. Moreover, estimation of parasitic resistances of capacitors and inductors provides information about the functional state of the dC-dC converter and forecasting future fails.

关键词： Uncertainty PI control Power system management Estimation dC-dC power converters Artificial neural networks microelectronics

来源：评论

学校读者我要写书评

暂无评论

A 10-MHz Three-Level Buck Converter with dual-Loop Time-Based Control and Flying Capacitor Voltage-Balance for Fast dVS

A 10-MHz Three-Level Buck Converter with Dual-Loop Time-Base...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： Gabriele Magni Paolo Melillo Alessandro Bertolini Mauro Leoncini Massimo Ghioni Politecnico di Milano DEIB Milan Italy STMicroelectronics AMG R&D Milan

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

High efficiency, small footprint and fast dynamic response are the key parameters of power management integrated circuits for portable applications. In this context, the three-level buck converter (TLBC) emerges as a practical solution, as it doubles the switching frequency and reduces the voltage swing at the switching node, compared to a conventional buck converter. As results, a small volume inductor can be employed, and high bandwidth can be achieved without compromising the converter's efficiency. However, precise regulation of the flying capacitor voltage at half the input supply is mandatory to ensure the reliable operation of the converter. This paper presents a dual-loop time-based control for a 10-MHz 2.8~3.6-V input and 0.6~ 1.2- V output TLBC. The proposed time-based controller merges the flying capacitor and the output voltage regulation in a single structure, thus minimizing the area occupation. The controller was designed in a 150-nm BCd technology. Simulations in SIMetrixlSIMPLIS demonstrates the efficacy and the robustness of the proposed control.

关键词： Buck converters Switching frequency Power system management Capacitors Switches Robustness Regulation

来源：评论

学校读者我要写书评

暂无评论

Bi-directional distributed Amplifier in 0.11 μm CMOS Technology

Bi-directional Distributed Amplifier in 0.11 μm CMOS Techno...

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： Merve Gölçek Yazıcı Asım Kepkep Metin Yazgı Department of Electronics and Communications Engineering Istanbul Technical University Istanbul Turkey Mikroelektronik Ltd. (MKR-IC) Istanbul Turkey

This paper presents and compares two different design approaches for bi-directional distributed amplifiers (BddA) in $0.11 \mu m$ CMOS technology. distributed amplifiers (dA) and BddAs can be designed starting from T-type and π- type unit cells of artificial transmission lines (ATL). This paper presents π- type topology for BddAs and compares with T-type BddAs in terms of gain, bandwidth and chip area. designing dAs and BddAs with π- type unit cells provide advantages from two different perspectives. Firstly, π- type BddAs can be designed with more g m - cells than T-type BddAs with the approximately same chip area. This provides higher gain without the cost of chip area because a π- type unit cell has one less inductor than a T-type unit cell. Secondly, smaller-sized g m - cells can be designed owing to extra active cells in π- type BddAs in order to increase the bandwidth of BddAs. Hence, π- type BddA can provide higher bandwidth with the same gain and the chip area if desired. The simulated gains of BddA with three T-type and four π- type unit cells are 8.5 dB and 10 dB at 2-19.5 GHz. In addition, BddA built using π- type unit cells with active cells equivalent to four fully active g m - cells is designed with smaller g m - cells to achieve higher bandwidth. Thus, 8.5 dB gain is obtained over 2-23 GHz. The chip areas are almost the same as the BddA with three T-type unit cells for all versions of designed π- type BddAs.

关键词：

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共84页 << < 7 8 9 10 11 12 13 14 15 16 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：