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检索条件"任意字段=Conference on Ph.D Research in Microelectronics and Electronics"

共 834 条记录，以下是11-20 订阅

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Computationally Efficient RF Band and Base band Beam-former for Coherent Plane Wave Imaging 19

Computationally Efficient RF Band and Base band Beam-former ...

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19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Alzein, Zahraa Crocco, Marco Cavighal, daniele d. Univ Genoa DITEN Dept I-16149 Genoa Italy Esaote SpA I-16152 Genoa Italy

ISBN: (纸本)9798350386301;9798350386318

This study presents computationally efficient implementations of radio frequency (RF) band and baseband receive beamforming and coherent compounding applied to multi-angle plane wave transmission. The impact of the sampling frequency on image quality has been measured by standard metrics on simulated data for both approaches. Moreover, the computational cost in terms of processing time and floating point operations has been evaluated. Finally, the memory and transfer bandwidth requirements have been estimated for both focalization data and acquired raw data. The results demonstrate that baseband beamforming can achieve acceptable image quality with a sampling frequency reduced roughly by a factor of 4 with respect to RF band beamforming. The consequent 4-fold reduction of required transfer bandwidth and memory storage for raw data comes at the cost of a mild increase in computational load of about 50%.

关键词： Coherent plane wave imaging Baseband Beamforming RF-band Beamforming Image Quality Computational Complexity

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Enhancing Electrical Ruggedness in double-Sided Cooled Power Modules 19

Enhancing Electrical Ruggedness in Double-Sided Cooled Power...

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19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Scognamillo, Ciro Catalano, Antonio Pio Codecasa, Lorenzo Castellazzi, Alberto d'Alessandro, Vincenzo Univ Federico II Dept Elect Engn & Informat Technol Naples Italy Politecn Milan Dept Elect Informat & Bioengn Milan Italy Kyoto Univ Adv Sci Solid State Power Proc SP2 Lab Fac Engn Kyoto Japan

ISBN: (纸本)9798350386301;9798350386318

This paper explores the electrical ruggedness of double-sided cooled (dSC) power modules by focusing on the influence of the spacing between interfacing substrates on the voltage endurance of the assembly. For the first time, it is suggested to fill the silicone gel surrounding the dies with barium titanate (BaTiO3) in this technology. The analysis relies on detailed numerical simulations performed with COMSOL Multiphysics. Results confirm the beneficial pushout effect dictated by a reduced spacing. Additionally, it is found that integrating BaTiO3 increases the critical voltages that the module can withstand before the breakdown onset.

关键词： Barium titanate (BaTiO3) double-sided cooled (dSC) power modules (PMs) electrical ruggedness insulating silicone gel

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design and Modellization of a Neural Network used to Optimize and to Monitor a dC-dC converter 19

Design and Modellization of a Neural Network used to Optimiz...

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19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Radhakrishnan, Sandeep Krishnan Nandialath Passi, Stefano Cabrini, Alessandro d'Angelo, Francesco Nicolosi, Alessandro Iannelli, Luca Univ Pavia Dept Ind & Informat Engn STMicroelect Pavia PV Italy STMicroelectronics Smart Power R&D Agrate Brianza MB Italy Univ Pavia Dept Ind & Informat Engn Pavia PV Italy

ISBN: (纸本)9798350386301;9798350386318

The purpose of this paper is to describe the model and the design of a neural network (NN) that optimizes a dC-dC converter power management system. The dC-dC converter plays a crucial role in maintaining the output voltage within the desired range. However, the conventional power management system has limitations in handling nonlinearities and uncertainties in the system. The proposed approach exploits the capability of a NN to accurately estimate certain parameters of the circuit that are closely associated with the functionality of the feedback control loop. In the case under analysis, we use Proportional-Integral-derivative (PId) control to regulate the output voltage. Precise estimation of the real value of analog components involved in the computation of PId parameters can improve the control loop and overall performance. Moreover, estimation of parasitic resistances of capacitors and inductors provides information about the functional state of the dC-dC converter and forecasting future fails.

关键词： Neural network power management estimation prevision failure optimization feedback monitoring

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A 10-MHz Three-Level Buck Converter with dual-Loop Time-Based Control and Flying Capacitor Voltage-Balance for Fast dVS 19

A 10-MHz Three-Level Buck Converter with Dual-Loop Time-Base...

引用

19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Magni, Gabriele Melillo, Paolo Bertolini, Alessandro Leoncini, Mauro Ghioni, Massimo Politecn Milan DEIB Milan Italy STMicroelectronics AMG R&D Milan Italy

ISBN: (纸本)9798350386301;9798350386318

High efficiency, small footprint and fast dynamic response are the key parameters of power management integrated circuits for portable applications. In this context, the three-level buck converter (TLBC) emerges as a practical solution, as it doubles the switching frequency and reduces the voltage swing at the switching node, compared to a conventional buck converter. As results, a small volume inductor can be employed, and high bandwidth can be achieved without compromising the converter's efficiency. However, precise regulation of the flying capacitor voltage at half the input supply is mandatory to ensure the reliable operation of the converter. This paper presents a dual-loop time-based control for a 10-MHz 2.8 similar to 3.6-V input and 0.6 similar to 1.2-V output TLBC. The proposed time-based controller merges the flying capacitor and the output voltage regulation in a single structure, thus minimizing the area occupation. The controller was designed in a 180-nm BCd technology. Simulations in SIMetrix/SIMPLIS demonstrates the efficacy and the robustness of the proposed control.

关键词： Three-Level Buck Converter Flying Capacitance Time-Based Control Voltage-balance

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Improvements Through Forward Power Transfer in an Isolated Flyback Boost Converter for Solar Applications 19

Improvements Through Forward Power Transfer in an Isolated F...

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19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Cruz-Cozar, Juan Medina-Garcia, Alfredo Perez-Martinez, Jorge Martos-Contreras, Cristina Rodriguez, Noel Morales, diego P. Infineon Technol AG R&D Funding Munich Germany Infineon Technol AG Power Syst Engn Munich Germany Univ Granada Elect & Comp Technol Granada Spain

ISBN: (纸本)9798350386301;9798350386318

The concept of distributed renewable energy systems brings with it the need for further research in power electronics. The use of local solar energy, with technologies such as microinverters and micro-optimizers, implies the need to raise voltages to adapt them to a distribution bus from which the rest of the elements operate. In this work, the resonant behavior of a forward-flyback boost is studied, which allows to obtain a higher energy density than in a conventional flyback. For this purpose, an exhaustive comparison is made in terms of energy between both proposals, showing how the addition of a forward behavior improves the performance. In addition to the theoretical comparison, a converter is made to operate under the same conditions transferring only energy in flyback mode as well as in forward-flyback mode. This demonstrates how higher power density can be obtained thanks to forward transfer through capacitors, devices with better energy density.

关键词： resonant flyback forward solar energy boost power density

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design of a Nano-Power Capacitor-Less LdO Voltage Regulator for Wake-Up Radio Applications 19

Design of a Nano-Power Capacitor-Less LDO Voltage Regulator ...

引用

19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Villa, Marco Guerrini, Marco Scarselli, Eleonora Franchi d'Addato, Matteo Elgani, Alessia Maria Nicolosi, Alessandro Rossi, Sandro Romani, Aldo ARCES DEI Univ Bologna Bologna Italy STMicroelectronics Bologna Italy STMicroelectronics Comaredo Italy

ISBN: (纸本)9798350386301;9798350386318

This paper presents a subthreshold capacitorless low-dropout (LdO) voltage regulator for powering a WakeUp Receiver (WuRX) in an ultra-low power IoT system. The system must maintain very low quiescent current to maximize the battery life of the node. Since the standby power consumption of the reference wake-up circuit is extremely low (< 55 nW), it is crucial that the LdO has even lower power consumption to avoid becoming the bottleneck of the entire system. The proposed LdO maintains a power consumption below 5 nW across the entire possible input voltage range from 0.7-V to 4.2-V, which includes the typical voltage range of lithium batteries. In nominal condition, with input voltage of 1.2 V, the power consumption is only 803 pW, accounting for less than 2% of the entire node. Circuit design was performed on an STmicroelectronics 90-nm CMOS technology and achieve low output voltage ripple in presence of the current profiles requested by the WuRX load, and temperature stability, while maintaining the above power consumption across possible process and temperature variations. Additionally, a transistor-level simulation of the entire circuit consisting of LdO and WuRX is reported, to demonstrate the correct functionality of the whole system.

关键词： LdO Power Management Wake-Up Receiver IoT Ultra-Low-Power

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An Accurate High-Voltage Supply-Referred Low-Impedance On-Chip Reference Voltage for Optimized driving of High-Side PMOS Transitors 19

An Accurate High-Voltage Supply-Referred Low-Impedance On-Ch...

引用

19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Zekorn, Tobias Schimkat, Florian Wehr, Erik Vohl, Kenny Weihs, Leon Wunderlich, Ralf Heinen, Stefan Rhein Westfal TH Aachen Integrated Analog Circuits & RF Syst Kopernikusstr 16 D-52074 Aachen Germany

ISBN: (纸本)9798350386301;9798350386318

This paper presents the design of a high-voltage supply-referred reference voltage as a high-side (HS) current sink for the power management unit and output driver of a Gate Shaper Integrated Circuit (GSIC) for Silicon-Carbide (SiC) power MOSFETs. In order to provide reproducible patterns at the gate of the power MOSFETs this current mode gate driver employs a fine resolution in time and current requiring fast transients for switching the currents. To provide fast transient currents cascode power transistors are driven with 5V drivers requiring an accurate supply-referred low-impedance reference voltage for sinking the charge of the driven gate. The reference voltage V-ref,V-LI is provided by this HV-reference to the gate of PMOS clamp transistors supplying the drivers with a low-impedance voltage sink of 15V at a 20V supply voltage and the capability of sinking currents of 50mA. The design has been fabricated on an area of 0.048mm(2) in a 0.18 mu m HV BCd technology and has been evaluated in simulations and measurements. Further, the design is implemented in a control loop with a dC power consumption of 167.8 mu A from 20V and 7.04 mu A from 5V supply voltage and a phase margin of 67.7 degrees.

关键词： high-voltage reference low-impedance reference supply-referred reference high-side driver PMOS-driver gate-driver switch mode power converter Gate-Shaping digital Gate driver

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An Impedance Characterisation Circuit for Implantable research Platforms 19

An Impedance Characterisation Circuit for Implantable Resear...

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19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Manatchinapisit, Vichaya Feng, Peilong Xie, Lijie Constandinou, Timothy G. Imperial Coll London Dept Elect & Elect Engn London SW7 2BT England Imperial Coll London UK Dementia Res Inst Care Res & Technol Ctr London England Mint Neurotechnol Ltd 125 Wood St London EC2V 7AW England

ISBN: (纸本)9798350386301;9798350386318

Neuromodulation devices use stimulation to inject current through electrodes to modulate the activity of tissue for therapeutic benefit. Complex electrochemical processes happening at the electrode-tissue interface pose a challenge in ensuring long-term safety to avoid corrosion and tissue damage. Convention devices such as deep brain stimulators (dBS) providing constant, tonic stimulation patterns can be designed to operate within a safe window by controlling parameters. Recent devices providing closed-loop stimulation, for example, dynamically adjusting stimulation based on neural activity. Furthermore, research platforms configure devices for new neural targets, and new therapies and can use different electrodes. To ensure safe operation and to mitigate potentially hazardous states, it is now essential to monitor electrode properties. Electrochemical impedance spectroscopy (EIS) is a valuable technique for characterizing electrode properties, such as charge transfer and surface integrity. This paper describes a circuit for achieving in situ characterisation of electrode impedance using EIS. The circuit generates and injects a microamp-level sinusoidal test current, measures the voltage waveform, and sweeps frequency to obtain an impedance spectrum. This has been implemented in an integrated circuit technology for future integration within an implantable research platform. The design has been verified through circuit simulation, using a realistic model for a dBS electrode that has been experimentally characterised.

关键词： Electrochemical impedance spectroscopy (EIS) electrode characterization implantable research platform

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drift-tolerant implementation of a neural network on a PCM-based Analog In-memory Computing unit for motor control applications 19

Drift-tolerant implementation of a neural network on a PCM-b...

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19th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Zavalloni, F. Antolini, A. Torres, M. L. Nicolosi, A. d'Angelo, F. Lico, A. Scarselli, E. Franchi Pasotti, M. Univ Bologna ARCES DEI Viale Carlo Pepoli 3-2 I-40123 Bologna Italy STMicroelectronics Viale Carlo Pepoli 3-2 I-40123 Bologna Italy STMicroelectronics Via Camillo Olivetti 2 I-20864 Agrate Brianza Italy STMicroelectronics Via Tolomeo 1 I-20007 Cornaredo Italy

ISBN: (纸本)9798350386301;9798350386318

Neural Networks (NN) are involved in a plethora of applications, such as gesture recognition and data labeling. In this scenario, Analog In-Memory Computing (AIMC) is a promising paradigm to deal with the prohibitive energy constraints and performance issues related to the NN implementation. As a proof of concept, this paper proposes a realization of a simple NN for a motor control driver through an AIMC unit based on an embedded phase-Change Memory (ePCM), both designed in a 90-nm CMOS STmicroelectronics technology. The accuracy of the NN inference is characterized in different scenarios to evaluate the influence of cells conductance drift in a real application. In particular, classification accuracy in both uncompensated and compensated cases is experimentally evaluated at several time intervals and considering different cells conductance levels. Results highlight that the proposed compensation method allow to obtain an accuracy above the 96% after 5 days from cells programming even with lower levels of conductance.

关键词： phase-change Memory (PCM) Analog Inmemory Computing (AIMC) Proportional-Integral-derivative (PId) Motor Control Artificial Intelligence

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Improving Performance of InGaP/GaAs HBT Arrays by means of Temperature-dependent Base Ballasting Resistors 18

Improving Performance of InGaP/GaAs HBT Arrays by means of T...

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18th International conference on ph.d research in microelectronics and electronics (PRIME)

作者： Scognamillo, Ciro Catalano, Antonio Pio d'Alessandro, Vincenzo Zampardi, Peter J. Burger, Kerry Univ Federico II Dept Elect Engn & Informat Technol Naples Italy Qorvo Inc Newbury Pk CA USA

ISBN: (纸本)9798350303209

Base ballasting resistors (BBRs) are commonly adopted to minimize electrothermal (ET) effects in arrays of bipolar transistors for power amplifier (PA) applications. In this paper, innovative BBRs with temperature-dependent resistivity are proposed in order to improve the trade-off between safe-operating area (SOA) and radiofrequency (RF) performances. As a simple case-study, a three-cell heterojunction bipolar transistor (HBT) fabricated by Qorvo is considered and circuital ET simulations are performed in AdS. Results of the comparison between the proposed strategy and the traditional one are discussed, thus providing useful insights into the advantages of temperature-dependent BBRs.

关键词： Base ballasting resistors (BBRs) electrothermal (ET) simulations gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) safe operating area (SOA)

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