A novel, complete analytical model is derived for the static behavior of a monotonic-switching differential charge-scaling AdC in terms of capacitor variations. Expressions derived for the transition voltages signific...
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ISBN:
(纸本)9781509004935
A novel, complete analytical model is derived for the static behavior of a monotonic-switching differential charge-scaling AdC in terms of capacitor variations. Expressions derived for the transition voltages significantly reduce the cost of AdC transfer curve simulation. Capacitor variations create no offset error. Full expressions are derived and linearized for the integral anddifferential nonlinearity errors. These expressions enable the calculation of the worst-case values in consideration of statistical process variations. The worst-case values provide suitable objective functions to consider in capacitor placement optimization.
With the possibility of fabricating single-photon avalanche diodes in standard CMOS processes, arrays for range imaging applications have been developed. Proper operation in high ambient illumination environments is o...
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ISBN:
(纸本)9781509004935
With the possibility of fabricating single-photon avalanche diodes in standard CMOS processes, arrays for range imaging applications have been developed. Proper operation in high ambient illumination environments is one of the major issues of scannerless sensors published so far. In this paper a theoretical study of the direct and indirect working principle regarding high ambient illumination is shown. Further, new concepts based on these principles to reduce the sensitivity to ambient light are presented.
Modern CMOS integrated technologies integrate a variety of complex multi-physics components which contribute a growing number of challenges in the circuit design. This paper is focused on the description of the requir...
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ISBN:
(纸本)9781509004935
Modern CMOS integrated technologies integrate a variety of complex multi-physics components which contribute a growing number of challenges in the circuit design. This paper is focused on the description of the requirements and technical aspects which should be considered for successful circuit design involving capacitive MEMS. To illustrate the process, the design of an input stage for a MEMS dielectric charge bipolar control method is presented.
This paper describes the linearity degradation effect in integrated circuits caused by the silicide contacts of polysilicon resistors. This secondary distorting effect starts to play a role when high system linearity ...
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ISBN:
(纸本)9781509004935
This paper describes the linearity degradation effect in integrated circuits caused by the silicide contacts of polysilicon resistors. This secondary distorting effect starts to play a role when high system linearity is required or the primary nonlinear components like transconductances are already optimized for low distortion. physical background is given with an emphasis on circuit design using RF pcells and the effect on the linearity figure-of-merit IIP3 of composite circuits is demonstrated. The influence on a practical highly linear broadband LNA employing Complementary derivative Superposition for Cognitive Radios is shown and recommendations to reduce or to use the effect is presented.
This paper presents an accurate yet compact model for vertical cavity surface emitting lasers (VCSEL), which can be extracted from simple dC and small-signal electro-optical measurements. Since VCSELs are the bottlene...
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ISBN:
(纸本)9781509004935
This paper presents an accurate yet compact model for vertical cavity surface emitting lasers (VCSEL), which can be extracted from simple dC and small-signal electro-optical measurements. Since VCSELs are the bottleneck of high-speed electro-optical transceivers, the model is essential in the design of high-speed laser drivers. VCSEL rate equations are used to describe the electrical to optical conversion in the laser, while non-linear parasitcs are modelling the VCSEL interface. The model is applied to a commercially available VCSEL and there is an excellent agreement between the simulated and measured eye diagrams at different data rates and bias currents.
The level of security provided by physically unclonable functions (PUFs) strongly depends on the unpredictability of its challenge-response behavior. Systematic variation in the properties of a PUF might introduce cor...
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ISBN:
(纸本)9781509004935
The level of security provided by physically unclonable functions (PUFs) strongly depends on the unpredictability of its challenge-response behavior. Systematic variation in the properties of a PUF might introduce correlations in the output bits. The mutual dependence of response bits is typically not detected by conventional methods, thus leaving the PUF vulnerable to prediction attacks. New methods accounting for the spatial distribution of response bits are presented, allowing to detect security leaks due to correlation effects at device level. The presented methods are easily applicable to a wide-range of array-based PUFs.
In analog layout design, chip floorplans are usually still handcrafted by human experts. Particularly, the nondiscrete variability of block dimensions must be exploited thereby, which is a serious challenge for optimi...
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ISBN:
(纸本)9781509004935
In analog layout design, chip floorplans are usually still handcrafted by human experts. Particularly, the nondiscrete variability of block dimensions must be exploited thereby, which is a serious challenge for optimization-based algorithmic floorplanners. This paper presents a fundamentally new automation approach based on self-organization, in which floorplan blocks can autonomously move, rotate anddeform themselves to jointly let compact results emerge from a synergistic flow of interaction. Our approach is able to minimize area and wirelength, supports nonslicing floorplan structures, can consider fully variable block dimensions, accounts for a fixed rectilinear boundary, and works absolutely deterministic. The approach is innovatively different from conventional, top-down oriented floorplanning algorithms.
The complexity and heterogeneity of today's mixed-signal systems makes verification a challenge. A particular challenge is the sensitivity of analog parts to variations in parameters, inputs, or initial conditions...
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ISBN:
(纸本)9781509004935
The complexity and heterogeneity of today's mixed-signal systems makes verification a challenge. A particular challenge is the sensitivity of analog parts to variations in parameters, inputs, or initial conditions. We present a methodology for formal verification of mixed-signal systems that verifies the impact of variations of parameters, inputs, or initial conditions on specified properties. Compared with state of the art, the proposed methodology can be integrated easily in existing design flows, handles analog anddigital parts, and offers improved scalability. The method is applied on a third order Sigma delta Modulator for verifying the stability property. The results show that our approach is using one simulation run able to find the input sequence that could lead to the undesired system behavior. These values are often not trivial and most likely would never be detected by traditional simulation-based techniques.
This paper presents the design of a multiphase clock generator that can be integrated in a current-mode wideband receiver. This block consists of a ring of dynamic transmission-gate flip-flops, which generates 8-phase...
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ISBN:
(纸本)9781509004935
This paper presents the design of a multiphase clock generator that can be integrated in a current-mode wideband receiver. This block consists of a ring of dynamic transmission-gate flip-flops, which generates 8-phase clocks non-overlapped with 12.5% duty-cycle, from an external input clock at eight times the desired output frequency. The circuit is designed using CMOS 65 nm technology with 1 V supply. Simulation results, for 1 GHz output clock, show that the phase error is 0.045 degrees, considering process and mismatch variations of the circuit, with a power consumption of 10 mW, allowing the receiver to achieve H R-3,R-5 > 60 dB for more than 95% of the Monte Carlo runs.
This paper presents a straightforward method of STF engineering in continuous-time Sigma delta modulators within the web-baseddesign tool ***. There are already different well known methods to obtain the STF dependin...
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ISBN:
(纸本)9781509004935
This paper presents a straightforward method of STF engineering in continuous-time Sigma delta modulators within the web-baseddesign tool ***. There are already different well known methods to obtain the STF depending on constraints given by the designer. One possibility is the analytical derivation of the high-level coefficients yielding a certain STF. Further, the Sigma delta modulator can be embedded into a filter with the desired characteristic or vice versa. However, as the NTF and STF are dependent upon each other, they cannot be chosen independently. The web-baseddesign tool for continuous-time Sigma delta modulators relies on a heuristic search based on a genetic algorithm that is able to determine a STF complying to given constraints while maximizing the signal-to-noise ratio of the chosen modulator architecture at the same time. This paper shows the capabilities of the publicly available design tool in regard of STF engineering and gives corresponding examples.
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