With the possibility of fabricating single-photon avalanche diodes in standard CMOS processes, arrays for range imaging applications have been developed. Proper operation in high ambient illumination environments is o...
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ISBN:
(纸本)9781509004942
With the possibility of fabricating single-photon avalanche diodes in standard CMOS processes, arrays for range imaging applications have been developed. Proper operation in high ambient illumination environments is one of the major issues of scannerless sensors published so far. In this paper a theoretical study of the direct and indirect working principle regarding high ambient illumination is shown. Further, new concepts based on these principles to reduce the sensitivity to ambient light are presented.
In this paper, a 3ddifferential delay line fabricated using a low temperature cofired ceramic (LTCC) technology is presented. The main feature of this component is its high value of delay density per unit area when c...
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ISBN:
(纸本)9781509004942
In this paper, a 3ddifferential delay line fabricated using a low temperature cofired ceramic (LTCC) technology is presented. The main feature of this component is its high value of delay density per unit area when compared with other differential geometries such as meanders, edge-coupled lines or twisted pair lines. An increase of a factor of 6 in the delay density is demonstrated, whereas distortion, attenuation and return loss are kept inside reasonable values.
In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed arc...
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ISBN:
(纸本)9781509004942
In this paper a reconfigurable implantable low noise amplifier for the recording of neural signals is presented. It is comprised by low-power and noise efficient current reuse OTAs in its direct path. The proposed architecture allows for an active feedback to set the high-pass corner in place of the commonly used pseudoresistor. Bandwidth selectivity is achieved by circuit reconfigurability which changes the pole frequencies of the system without impacting the total power consumption. Simulation results in AMS 0.18μm technology validate the proposed architecture in both nominal and corner process conditions with an estimated total power consumption of 454nW.
Extensive knowledge of the protection device's behavior under electrostatic discharge stress is mandatory to characterize protective elements and systems. This paper gives a brief overview on different electrostat...
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ISBN:
(纸本)9781509004942
Extensive knowledge of the protection device's behavior under electrostatic discharge stress is mandatory to characterize protective elements and systems. This paper gives a brief overview on different electrostatic discharge protection concepts, including general considerations on diverting stress, trigger mechanisms, and their limitations. The protection approaches have to be selected in conjunction with the operational signals to avoid malfunction, increased power consumption, or physical failure. The Wunsch-Bell model is extended by means of an additional axis incorporating the rise time to better characterize different protective circuitry from component- to system-level. This allows for more accurate prediction of system robustness possibly preventing costly re-designs.
Modern CMOS integrated technologies integrate a variety of complex multi-physics components which contribute a growing number of challenges in the circuit design. This paper is focused on the description of the requir...
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ISBN:
(纸本)9781509004942
Modern CMOS integrated technologies integrate a variety of complex multi-physics components which contribute a growing number of challenges in the circuit design. This paper is focused on the description of the requirements and technical aspects which should be considered for successful circuit design involving capacitive MEMS. To illustrate the process, the design of an input stage for a MEMS dielectric charge bipolar control method is presented.
This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signa...
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This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. The low area and power consumptions make the processor an extremely scalable device which would work well in closed loop neural prosthesis for the treatment of neural diseases.
This paper introduces a new concept of liquidphase inkjet-based fabrication process for low cost, low range and high throughput Radio Frequency Identification (RFId) tags. In this research, passive chips have one pad...
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ISBN:
(纸本)9781509004942
This paper introduces a new concept of liquidphase inkjet-based fabrication process for low cost, low range and high throughput Radio Frequency Identification (RFId) tags. In this research, passive chips have one pad on the top of the chip and the back of the silicon die (bulk) acting as the second pad. Such a chip can be delivered, using an inkjet-based process, onto one pad of an antenna instead to be precisely placed using flip-chip method. This allows producing RFId tag only with printing steps, reducing considerably the assembly and hence the overall costs. We demonstrate the feasibility of this approach by analyzing the capacitive coupling obtained using double-surface chips.
In this paper we present an efficient model for current calculation through silicon nanocrystals. The model uses self consistent field approach to calculate the evolution of transmission spectra and Landauer formalism...
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ISBN:
(纸本)9781509004942
In this paper we present an efficient model for current calculation through silicon nanocrystals. The model uses self consistent field approach to calculate the evolution of transmission spectra and Landauer formalism for current calculations. We implemented the split in spectra for different spin so that the model works in case of coulomb blockade. A few simulations were performed using a physical simulator to extract parameters to be inserted in model. The current voltage characteristics were calculated from the model for structures with different geometry and coupling strength between the lattice and contacts. The results from the model show good accordance with those from physical simulator and are obtained with more than two orders of magnitude speed up.
The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them i...
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ISBN:
(纸本)9781509004942
The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery properties and complexity. We show that energy recovery achievable depends on the tank-capacitor size. We also show that tank-capacitor sizes can be reduced as their number increases concluding that combined tank capacitance (CTT) versus load capacitance (CL) ratio is the significant parameter. We propose that using a CTT/CL ratio of 10 and using a 4-step charging power-clock constitute appropriate trade-offs in practical circuits.
In analog layout design, chip floorplans are usually still handcrafted by human experts. Particularly, the nondiscrete variability of block dimensions must be exploited thereby, which is a serious challenge for optimi...
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In analog layout design, chip floorplans are usually still handcrafted by human experts. Particularly, the nondiscrete variability of block dimensions must be exploited thereby, which is a serious challenge for optimization-based algorithmic floor-planners. This paper presents a fundamentally new automation approach based on self-organization, in which floorplan blocks can autonomously move, rotate anddeform themselves to jointly let compact results emerge from a synergistic flow of interaction. Our approach is able to minimize area and wirelength, supports nonslicing floorplan structures, can consider fully variable block dimensions, accounts for a fixed rectilinear boundary, and works absolutely deterministic. The approach is innovatively different from conventional, top-down oriented floorplanning algorithms.
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