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检索条件"任意字段=Conference on Ph.D Research in Microelectronics and Electronics"

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STF engineering in CT sigma-delta modulators using ***

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ph.d. research in microelectronics and electronics (PRIME)

作者： Johannes Wagner Rudolf Ritter Maurits Ortmanns Institute of Microelectronics University of Ulm Ulm Germany

ISBN: (纸本)9781509004942

This paper presents a straightforward method of STF engineering in continuous-time ΣΔ modulators within the web-based design tool ***. There are already different well known methods to obtain the STF depending on constraints given by the designer. One possibility is the analytical derivation of the high-level coefficients yielding a certain STF. Further, the ΣΔ modulator can be embedded into a filter with the desired characteristic or vice versa. However, as the NTF and STF are dependent upon each other, they cannot be chosen independently. The web-based design tool for continuous-time ΣΔ modulators relies on a heuristic search based on a genetic algorithm that is able to determine a STF complying to given constraints while maximizing the signal-to-noise ratio of the chosen modulator architecture at the same time. This paper shows the capabilities of the publicly available design tool in regard of STF engineering and gives corresponding examples.

关键词： digital-analog conversion Signal to noise ratio design tools Optimization Genetic algorithms Frequency modulation

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delta compression in time-multiplexed multichannel neural recorders

Delta compression in time-multiplexed multichannel neural re...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Matteo Pagin Michael Haas Joachim Becker Maurits Ortmanns Institute of Microelectronics Unversity of Ulm Ulm Germany

ISBN: (纸本)9781509004942

In this paper we analyze the effectiveness of a serial delta compression scheme for reducing data rate of neural signals in brain implanted systems. due to their location neural implants have limited power budget in order not to damage the surrounding tissues. In an implant with a wireless communication link the data rate needs then to be reduced to meet the power requirements since the transmitter power consumption is often a dominating factor. In this paper we propose and analyze a digital delta compression scheme for multichannel implants which reduces the number of registers and offers more flexibility compared to the canonical scheme. Instead of subtracting from samples belonging to one channel we explore the possibility of using samples from different but correlated channels, this removes the need of storing previous samples for all channels. Synthesized and recorded data sets are used to investigate the effectiveness of the method together with a spike sorting program, to also evaluate the quality of the reconstructed signals.

关键词： Principal component analysis Sorting Neurons Registers Noise measurement Implants Power demand

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Multilevel outphasing power amplifier system with a transmission-line power combiner

Multilevel outphasing power amplifier system with a transmis...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Mikko Martelius Kari Stadius Jerry Lemberg Tero Nieminen Enrico Roverato Marko Kosunen Jussi Ryynänen Lauri Anttila Mikko Valkama Department of Micro- and Nanosciences Aalto University Espoo Finland Department of Electronics and Communications Engineering Tampere University of Technology Tampere Finland

This paper presents a multilevel outphasing power amplifier (PA) system consisting of eight class-d unit PAs on 28 nm CMOS and an off-chip transmission-line power combiner. The combiner, implemented on PCB with microstrip lines, was designed to operate at 1.8 GHz frequency and filter out the third and fifth harmonics generated by the PAs. The combiner layout was designed so that the line spacing increases towards the output to reduce coupling, while the lines are equal in length. The simulated maximum output power is 32.3 dBm (1.71 W) with an efficiency of 34.4%. With 20 MHz and 100 MHz LTE signals, average efficiencies of 15.2% and 15.1% were achieved, respectively.

关键词： Power combiners Power harmonic filters Harmonic analysis Wires Capacitors Power amplifiers

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A study on op-amp nonlinearity in a single-bit CT ΔΣ modulator employing GBW compensation

A study on op-amp nonlinearity in a single-bit CT ΔΣ modul...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Chao Chu Johannes Wagner Ahmad Al Marashli Jiazuo Chi Maurits Ortmanns Institute of Microelectronics University of Ulm Ulm Germany

ISBN: (纸本)9781509004942

This work investigates the nonlinear effect of the 1 st operational amplifier (op-amp) in a CT ΔΣ modulator with finite gain-bandwidth product (GBW) compensation. A behavioral op-amp model employing a hyperbolic tangent expression has been created and verified to approximate the op-amp nonlinear characteristics. In analyzing transient simulations of ΔΣ modulators compensated for different GBWs, the influence of the 1 st op-amp nonlinearity has been studied, indicating that more stringent linearity requirement on the 1 st op-amp must be satisfied in the modulator compensated for lower GBW. This issue can be addressed by increasing the op-amp dC gain, or by employing a mixed feedforward/feedback (FF/FB) architecture, which outperforms the cascade of integrators with feedback (CIFB) topology concerning linearity due to the reduced internal swing, thus allowing both GBW compensation and relaxed linearity requirements.

关键词： Linearity Gain Frequency modulation Topology distortion Signal to noise ratio

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design of ultra low power cascaded inductorless LNA for Wireless Sensor Network application

Design of ultra low power cascaded inductorless LNA for Wire...

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ph.d. research in microelectronics and electronics (PRIME)

作者： S.Vahid M. Bonehi Arthur Ruder Soheil Aghaie Iyappan Subbiah Ralf Wunderlich Stefan Heinen Integrated Analog Circuits and RF Systems RWTH Aachen University Germany

ISBN: (纸本)9781509004942

This paper presents a cascaded ultra low power LNA structure. The proposed architecture benefits from a common gate LNA as the first stage followed by inductorless common source LNA. The complete design was implemented in a standard 130nm RF CMOS process. The design occupies 130μm × 130μm active area. The circuit operates at 2.4GHz and draws 240μm under supply voltage of 1.2V. It shows active voltage gain of 42 dB and NF of 11.2 dB after post layout simulation. Thanks to first stage common gate structure, it has input reflection coefficient better than 22 dB.

关键词： Gain Impedance matching Logic gates Transistors Active inductors Low-power electronics Layout

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A comprehensive Verilog-A behavioral model of Spin-Transfer Torque memory cell

A comprehensive Verilog-A behavioral model of Spin-Transfer ...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Yilkal A. Belay A. Cabrini G. Torelli Department of Electronics University of Pavia Pavia Italy

ISBN: (纸本)9781509004942

Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for universal memory. An electrical model of STT-RAM cell is needed to adequately explore the design space of the device. In this paper, a comprehensive and compact Verilog-A behavioral model of STT-RAM cell is presented. The model captures both dynamic switching aspects and static properties of the magnetic tunnel junction (MTJ), which is the basic storage device in the STT-RAM cell. The dynamic switching behavior is modeled using Bernoulli random binary number generator in combination with switching probability function. The static behavior was represented by means of a variable resistor with bias current/voltage dependent low- and high- resistance values. In addition to its compactness and comprehensiveness, the model is suited to be used within standard integrated circuit CAd tools for analog and mixed-signal design simulation.

关键词： Switches Solid modeling Magnetic tunneling Magnetization Resistance Integrated circuit modeling Mathematical model

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Precoder and decoder for duobinary modulation over equalized 50-m SI-POF

Precoder and decoder for duobinary modulation over equalized...

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ph.d. research in microelectronics and electronics (PRIME)

作者： J. Aguirre C. Sánchez-Azqueta E. Guerrero C. Gimeno S. Celma Group of Electronic Design — Aragón Institute of Engineering Research (GDE I3A) Universidad de Zaragoza Zaragoza Spain

ISBN: (纸本)9781509004942

This work presents a novel CMOS transceiver that enables 50-m 1-mm step-index plastic optical fiber (SI-POF) to increase transmitted data rate up to 3.125 Gbps using amplitude duobinary modulation, in addition to continuous-time equalization. For that purpose, a duobinary precoder and a duobinary decoder have been designed in a cost-effective 0.18-μm CMOS technology fed with 1.8 V, consuming 27.9 mW in total. Additionally, a new model based on low-pass Bessel filter has been proposed to simulate the effect of the equalized channel, achieving excellent agreement with experimental data. Post-layout results validate the advantages of the proposed transceiver.

关键词： Modulation CMOS integrated circuits Optical signal processing decoding Logic gates Bandwidth CMOS technology

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A chip-level post-CMOS via-last Cu TSV process for multi-layer homogeneous 3d integration

A chip-level post-CMOS via-last Cu TSV process for multi-lay...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Seniz E. Kucuk Eroglu Yeong Cho Woo Yusuf Leblebici Ecole Polytechnique Federale de Lausanne Lausanne VD CH Samsung Electronics Seoul Korea Ecole Polytechnique Federal de Lausanne (EPFL) Lausanne Switzerland

In this paper, a die-level CMOS post-processing scheme for 3d integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The proposed process flow is used to fabricate a 4-layer chip stack using homogeneous CMOS memory chips. Electrical measurements are carried out to determine the resistance value of the TSVs. Kelvin bridge method is used in order to eliminate the additional resistance introduced by the experimental setup, and the average resistance value of a single TSV is determined as 180 mΩ. The current carrying capability is also investigated for possible electrical failures. It is concluded that the TSVs can carry up to 1.5 A (dC) current values without any failure.

关键词： Three-dimensional displays Through-silicon vias Etching CMOS integrated circuits Bonding Stacking Current measurement

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Large area silicon photomultipliers allow extreme depth penetration in time-domain diffuse optics

Large area silicon photomultipliers allow extreme depth pene...

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ph.d. research in microelectronics and electronics (PRIME)

作者： E. Martinenghi A. dalla Mora L. di Sieno S. Konugolu Venkata Sekar d. Contini A. Pifferi Dipartimento di Fisica Politecnico di Milano Milano Italy

ISBN: (纸本)9781509004942

We present the design of a novel single-photon timing module, based on a Silicon photomultiplier (SiPM) featuring a collection area of 9 mm2. The module performs Single-photon Timing Resolution of about 140 ps, thus being suitable for diffuse optics application. The small size of the instrument (5 cm × 4 cm × 10 cm) allows placing it directly in contact with the sample under investigation, maximizing that way the signal harvesting. Thanks to that, it is possible to increase the source detector distance up to 6 cm or more, therefore enhancing the penetration depth up to an impressive value of 4 cm and paving the way to the exploration of the deepest human body structures in a completely non-invasive approach.

关键词： detectors photonics Timing Instruments Time-domain analysis Optics Optical variables measurement

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design of a low phase error multiphase clock generator for modern wideband receivers

Design of a low phase error multiphase clock generator for m...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Miguel d. Fernandes Luis B. Oliveira João Goes João P. Oliveira Dept. of Electrical Engineering (DEE) Universidade Nova de Lisboa (UNL) Caparica Portugal

This paper presents the design of a multiphase clock generator that can be integrated in a current-mode wideband receiver. This block consists of a ring of dynamic transmission-gate flip-flops, which generates 8-phase clocks non-overlapped with 12.5% duty-cycle, from an external input clock at eight times the desired output frequency. The circuit is designed using CMOS 65 nm technology with 1 V supply. Simulation results, for 1 GHz output clock, show that the phase error is 0.045°, considering process and mismatch variations of the circuit, with a power consumption of 10 mW, allowing the receiver to achieve HR 3,5 > 60 dB for more than 95% of the Monte Carlo runs.

关键词： Receivers Clocks Power demand Harmonic analysis Wideband Mixers Generators

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