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检索条件"任意字段=Conference on Ph.D Research in Microelectronics and Electronics"

共 834 条记录，以下是311-320 订阅

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4-phase resettable quasi-adiabatic flip-flops and sequential circuit design

4-phase resettable quasi-adiabatic flip-flops and sequential...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Sachin Maheshwari V.A. Bartlett Izzet Kale Applied DSP and VLSI Research Group University of Westminster London United Kingdom

ISBN: (纸本)9781509004942

Resettable adiabatic flip-flops are essential in the design of adiabatic counters, thus, a comprehensive study for IECRL, PFAL and EACRL 4-phase quasi-adiabatic logic families have been done in this paper. In addition, a new resettable quasi-adiabatic flip-flop circuit is proposed for each of them. Using the non-resettable and the proposed resettable adiabatic flip-flops, a practical sequential circuit comprising of a 2-bit twisted ring counter is designed and the energy consumption, for four distinct states, at different ramping times is measured. The simulation results show that the energy consumption of the resettable counter is comparable with its non-resettable counterparts. Moreover, amongst the adiabatic logic used, the PFAL based implementation of both the non-resettable and the resettable counters exhibits the least energy consumption at all ramping times.

关键词： Adiabatic Radiation detectors Flip-flops Energy consumption Transistors Resistance Sequential circuits

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design of a 64 channels current-to-frequency converter ASIC, front-end electronics for high intensity particle beam detectors

Design of a 64 channels current-to-frequency converter ASIC,...

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ph.d. research in microelectronics and electronics (PRIME)

作者： F. Fausti G. Mazza F. Marchetto R. Sacchi R. Cirio Physics Department Turin University Turin Italy National Institute of Nuclear Physics Turin Italy

ISBN: (纸本)9781509004942

A new wide-input dynamic range, 64-channels current-to-frequency converter ASIC has been designed and is now under characterization. This chip, nicknamed TERA09, has been realized to equip the front-end readout electronics for the new generation of beam monitor chambers for particle therapy applications. In this field, the trend in the accelerator development is moving toward compact solutions providing high-intensity pulsed-beams. However, such a high intensity will saturate the present readout of the beam monitor chambers. In order to deal with the technology innovations in the particle therapy, the chip described in this work is able to cope with a higher maximum intensity while keeping high resolution by working on a six orders of magnitude conversion-linearity zone (hundreds of pA to hundreds of μA), with a gain spread in the order of 1-3% (r.m.s.), with a 200fC charge resolution.

关键词： Registers Application specific integrated circuits Radiation detectors Clocks Laser beams Particle beams Medical treatment

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Boost converter with load dependent adaptive controller for improved transient response

Boost converter with load dependent adaptive controller for ...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Samuel Quenzer-Hohmuth Steffen Ritzmann Thoralf Rosahl Bernhard Wicht Robert Bosch Center for Power Electronics Reutlingen University Reutlingen Germany Robert Bosch GmbH Reutlingen Germany

ISBN: (纸本)9781509004942

Size and cost of a boost converter can be minimized by reducing the voltage overshoot and fastening the transient response in case of load transient. The presented technique improves the transient response of a current mode controlled boost converter, which usually suffers from bandwidth limitation because of its right-half-plane zero (RHPZ). The proposed technique comprises a load current estimation which works as part of a digital controller without any additional measurements. Based on the latest load estimation the controller parameters are adapted, achieving small voltage overshoot and fast transient response. The presented technique was implemented in a digital control circuit, consisting of an ASIC in a 110 nm-technology, a Xilinx Spartan-6 field programmable gate array (FPGA), and a TI-AdS8422 analog-to-digital-converter (AdC). Simulation and measurements of a 4V-to-6.3V, 500mA boost converter show an improvement of 50% in voltage overshoot and response time to load transient.

关键词： Resistance Voltage control Frequency control Transient response Transient analysis Estimation Inductors

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A Tone Mapping algorithm suited for analog-signal real-time image processing

A Tone Mapping algorithm suited for analog-signal real-time ...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Lan Shi david Hadlich Christopher Soell Thomas Ussmueller Robert Weigel Institute for Electronics Engineering University of Erlangen-Nuremberg Erlangen Germany Institute for Mechatronics University of Innsbruck Innsbruck Austria

ISBN: (纸本)9781509004942

This work presents a Tone Mapping Operator (TMO) which adjusts the High dynamic Range (HdR) of image sensor data to the limited dynamic range of conventional displays with analog signal processing. It is based on photographic Tone Reproduction (PTR) and suitable for analog circuit design in a CMOS image sensor in order to reduce the hardware cost and operation time for real-time image processing. For this reason, the characteristic advantage and calculation limitation of analog technology are considered in the TMO algorithm proposal. Furthermore, the appropriate modelling is built and simulated in Verilog-A. The function of the algorithm is feasible for analog processing. The frequency of the analog TMO is upper 52MHz while it consumes 55mW. The simulation results of test images are compared with the digital global TMO and the proposed analog TMO provides a reasonable similar dynamic range compression.

关键词： Signal processing algorithms Image sensors Algorithm design and analysis dynamic range Analog circuits Image processing Real-time systems

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gPCdS: An interactive tool for creating schematic module generators in analog IC design

gPCDS: An interactive tool for creating schematic module gen...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Matthias Greif daniel Marolt Juergen Scheible Robert Bosch Center for Power Electronics Reutlingen University Reutlingen Germany

ISBN: (纸本)9781509004942

Optimization-based design automation for analog ICs still remains behind the demands. A promising alternative is given by procedural approaches such as parameterized generators, also known as PCells. We are working on a complete analog design flow based on parameterized generators for entire circuits and corresponding layout modules. Because the conventional programming of such enhanced generators is far too complicated and costly, new methods are needed to ease their development. This paper presents gPCdS (graphical PCdS), a novel tool for a designer-oriented development of schematic module generators, integrated into a common schematic entry environment. The tool is based on PCdS (Parameterized Circuit description Scheme), a meta-language for the creation of parametrized analog circuits. Schematic module generators are a very desirable complement to layout module generators in order to achieve a seamless schematic-driven layout design flow on module level. By facilitating a way of generator development that matches a design expert's mentality, gPCdS contributes to close this gap in the analog design flow.

关键词： Generators Layout Topology Integrated circuits Shape Algorithm design and analysis design automation

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A 10 bit A-to-d converter development within power optimized BCd technology

A 10 bit A-to-D converter development within power optimized...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Antonio d'Amico Florian Brugger dieter Härle Luca Petruzzi Andrea Baschirotto Dep. Of Physics University of Milano-Bicocca Milan Italy KAI Villach Austria Infineon Technology Villach Austria

This paper presents the development of a 10b AdC dedicated to the digitalization of a sensing current within advanced automotive applications. The presented AdC has been developed in a power optimized BCd technology, i.e. a process specifically optimized for power delivery and featuring signal processing capabilities. However it presents some limitations, i.e. highly non-linear capacitances, large mismatch, etc.. In this scenario a 10b AdC has been developed by means of a customized MATLAB model enabling the target performance achievements. The aim of this work is to study the effect of non-ideal components on the conversion performances focusing in particular on the technology limitations, like capacitors non-linearity and components mismatch. In order to achieve this, a Matlab model has been developed and then a demonstrator circuit has been designed at transistor level.

关键词： Capacitors Pipelines Mathematical model Clocks MATLAB Transistors Jitter

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Calculation of very near field radiated emission of a straight cable harness

Calculation of very near field radiated emission of a straig...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Herbert Hackl Bernhard Auinger NXP Semiconductors Austria Gratkorn Austria Institute of Electronics Graz University of Technology Graz Austria

ISBN: (纸本)9781509004942

Radiated emissions generated by an integrated circuit (IC) during operation must not exceed specific limits. For automotive ICs this is verified by the standardized ALSE (Absorber Lined Shielded Enclosure) measurement setup defined in the CISPR 25 standard. This test especially targets the E-field emitted by a long cable harness attached to the device under test. Apart from simulations, analytical calculation models can be applied to quickly estimate the compliance test results. Typically the Hertzian dipole antenna model is used to calculate the electric field radiating from cables. But during the ALSE test radiated emissions from 150 kHz to 1GHz are measured in 1m distance. This results in very near field conditions for the lower frequencies, where the common prediction model is at its theoretical limits. As an alternative this paper demonstrates an electrostatic approach. For the frequency range of 100 kHz to 30MHz constant transmission factors are derived which yield the radiated emission spectrum when applied to the IC's output signal spectrum. The results of both calculation models are compared to measurement data.

关键词： Frequency measurement dipole antennas Antenna measurements Wires Electrostatic measurements Integrated circuits Receiving antennas

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Class-O power amplifier with enhanced linearity using floating body technique in 130 nm standard CMOS technology

Class-O power amplifier with enhanced linearity using floati...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Muhammad Abdullah Khan Renato Negra Chair of High Frequency Electronics RWTH Aachen University Aachen Germany

ISBN: (纸本)9781509004942

In this paper, we present a modified class-O power amplifier (PA) which employs floating-body technique to achieve high linearity. Class-O is a new PA topology which incorporates two sub-amplifiers working in parallel to achieve high linearity and efficiency. The two sub-amplifiers are operated in common drain (Cd) and common source (CS) configuration. The proposed floating-body technique is verified with on-wafer measurements on single power transistors. The simulation results of overall class-O amplifier show a 2.3 dB improvement in output 1 dB compression point (P out1dB ) over the conventional body shorted to source version of the amplifier. The power added efficiency (PAE) of proposed class-O is 33.3% as compared to 24% for conventional version. Hence, enabling the proposed amplifier to transmit higher linear output power with more efficiency. The operating frequency of both the amplifiers 960MHz and the technology used is UMC 130nm standard RFCMOS.

关键词： MOS devices Linearity Standards CMOS integrated circuits Logic gates Capacitance Resistors

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An a VLSI driving circuit for memristor-based STdP

An a VLSI driving circuit for memristor-based STDP

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ph.d. research in microelectronics and electronics (PRIME)

作者： Simone Acciarito Alessandro Cristini Luca di Nunzio Gaurav Mani Khanal Gianluca Susi Department of Electronics Engineering University of Rome “Tor Vergata” Rome IT

ISBN: (纸本)9781509004942

The main goal in realizing a VLSI (analog VLSI) systems able to mimic functionalities of biological neural networks is pointed to the reproduction of realistic synapses. Indeed, because of the relative high synapse/neuron ratio, especially in the case of extremely dense networks (i.e., reproduction of a real scenario), synapses represent a considerable limitation in terms of waste of silicon area and power consumption as well. Thanks to advancement made in the implementation of memristor, the interest in bio-inspired neural network design has been renewed. Memristors have tunable resistance which depends on its past state; this is analogous to the operating mode of biological synapses. In this paper, we present the circuit implementation of a simple memristor-based neural network. Here, we propose a driving circuit model that not requires specific shape input pulses to change the memristor conductance (i.e., synaptic strength), but it can be driven by arbitrary shaped input pulses. Moreover, this prototype circuit offers the chance of emulating the standard STdP behavior allowing “controlled” changes for the synaptic weights. Some preliminary experimental results are reported to validate the proposed driving circuit.

关键词： Memristors Neurons Biological system modeling Integrated circuit modeling Mathematical model Timing Shape

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A bio-inspired reconfigurable architecture for Local Binary descriptors

A bio-inspired reconfigurable architecture for Local Binary ...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Selman Ergünay Yusuf Leblebici Ecole Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland

ISBN: (纸本)9781509004942

Limited resources of embedded devices and increased real time constraints have raised interest to the binary description methods over the floating-point ones such as SIFT and SURF in computer vision applications. Although many software applications of the binary descriptors are developed, there are few studies on their hardware implementations in the literature. despite the fact that direct hardware implementation of the algorithms can enhance the performance of calculations, flexible architectures which are able to support new approaches remain still an issue. At this point, mimicking biological neural network which has naturally capable of extracting features can offer different insights to the problem. In this paper we propose a reconfigurable architecture and its' hardware implementation for local binary description applications, inspiring from the biological neural network structures. Specifically, this architecture is based on the Cellular Neural Network (CNN), with two different types of cells which show either inhibitory or excitatory behaviour. Imposed restrictions on classical CNN architecture lead a multiplier-less area-efficient realization, while keeping the necessary flexibility. This network can be configured as an accelerator unit of the local binary descriptors in embedded vision applications.

关键词： Hardware Computer architecture Biological neural networks Retina Field programmable gate arrays Network architecture Cellular neural networks

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