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检索条件"任意字段=Conference on Ph.D Research in Microelectronics and Electronics"

共 834 条记录，以下是321-330 订阅

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CMOS high-performance UWB active inductor circuit

CMOS high-performance UWB active inductor circuit

引用

ph.d. research in microelectronics and electronics (PRIME)

作者： H.G. Momen M. Yazgi R. Kopru A.N. Saatlo Electrical-Electronics Eng. Dep. Istanbul Technical University Istanbul Turkey Electrical-Electronics Eng. Dep Isik University Istanbul Turkey Islamic Azad University Urmia Iran

ISBN: (纸本)9781509004942

In order to maximize efficiency of the designed gyrator-based active inductor, advanced circuit techniques are used. Loss and noise are most important features of the AIs, where they should be low enough to have high-performance device. The gyrator-C topology is used to design a new low-loss and low-noise active inductor. The gyrator-C topology is potentially high-Q and all transistors are utilized in common-source configuration to have high impedance in input-output nodes. All transistors are free of body effect. The p-type differential pair input transistors and the feed forward path are employed to decrease noise of the proposed circuit. Additionally, inductance value and quality factor are adjusted by variation bias current which gives to the device tunable capability. HSPICE simulation results are presented to verify the performance of the circuit, where the 180 nm CMOS process and 1.8 V power supply are used. The noise voltage and power dissipation are less than 2.8 nV/ √ Hz and 1.3 mW, respectively.

关键词： Artificial intelligence Active inductors Transistors CMOS integrated circuits Q-factor Simulation Topology

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Thermal issues in deep sub-micron FdSOI circuits

Thermal issues in deep sub-micron FDSOI circuits

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ph.d. research in microelectronics and electronics (PRIME)

作者： Can Baltacı Yusuf Leblebici Ecole Polytechnique Federale de Lausanne Lausanne VD CH Microelectronic Systems Laboratory École Polytechnique Fédérale de Lausanne

ISBN: (纸本)9781509004942

Self-heating effects became more prominent with the introduction of the modern devices like FdSOI and low thermal conductivity materials such as SiO2. Consequently, the design of high speed digital circuits which are the time-critical blocks of high performance processors started to be limited mainly by thermal issues. For observing the thermal behaviour of FdSOI structure on circuit level, a 64-bit Kogge-Stone parallel prefix adder is designed and implemented in 40nm bulk CMOS technology and thermal model of the circuit is extracted and simulated according to FdSOI design parameters. The implemented adder circuit has a critical path delay of 148ps under 900 mV power supply voltage with a power consumption of 12mW. The temperature profile of the designed circuit is extracted with thermal simulations and the peak temperature locations are examined in detail. The hot spot locations and their temperature values are correlated with the power density. It is shown that self-heating of high power density devices has a significant influence on the peak temperature of a design. Finally, a simple design solution is proposed which can significantly decrease the peak temperature.

关键词： density measurement Power system measurements Heating Adders Power dissipation Performance evaluation Thermal conductivity

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ALd-based 3d-capacitors for harsh environments

ALD-based 3D-capacitors for harsh environments

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ph.d. research in microelectronics and electronics (PRIME)

作者： dorothee dietz Yusuf Celik Andreas Goehlich Holger Vogt Fraunhofer Institute for Microelectronic Circuits and Systems IMS Duisburg Germany

ISBN: (纸本)9781509004942

Passive components like capacitors for harsh environments become more and more important, e. g. in the field of deep drilling, aerospace or in the automotive industry. They have to withstand temperatures up to 300 °C with a good performance concerning leakage current, breakdown voltage and capacitance density. The whole process flow has to be CMOS-compatible in order to offer the possibility for CMOS-integration. A highly n-doped Si-substrate (doping concentration about 10 20 cm -3 , phosphorus) acts as bottom electrode to keep the process flow as simple as possible. The capacitors are 3d-integrated to achieve a high capacitance density. For the dielectric layer and the upper electrode, atomic layer deposited (ALd) materials are used. The combination of the medium- and high-k dielectrics and the electrode materials are optimized, as well as some of the ALd-processes, to reach an optimum in leakage current and breakdown voltage. At a bias voltage of 3 V at room temperature, the leakage current amounts about 5 pA/mm 2 , at 300 °C about 40 pA/mm 2 . Up to ± 15 V for room temperature, respectively up to ± 10 V for 300 °C, no soft-breakdown is observed, indicating the absence of significant Fowler-Nordheim tunneling.

关键词： Leakage currents Capacitors Capacitance Electrodes Aluminum oxide Annealing

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Apodization scheme for hardware-efficient beamformer

Apodization scheme for hardware-efficient beamformer

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ph.d. research in microelectronics and electronics (PRIME)

作者： A. Ibrahim F. Angiolini M. Arditi J.-P. Thiran G. de Micheli LSI École Poly technique Fédérale de Lausanne (EPFL) Switzerland LTS5 École Poly technique Fédérale de Lausanne (EPFL) Switzerland Department of Radiology University of Lausanne (UNIL) Switzerland

ISBN: (纸本)9781509004942

3d ultrasound is an emerging diagnostic technique that extends standard ultrasound imaging by capturing volumes, instead of planes. This brings completely new diagnostic opportunities, among which the possibility of disjoining image acquisition and analysis, thus enabling remote diagnosis, which would bring obvious medical and economic benefits. Unfortunately, 3d ultrasound is several orders of magnitude more computationally complex than 2d imaging. Therefore, algorithmic improvements to simplify the processing are mandatory in order to conceive cheap, portable, low-power imagers. The kernel of the 3d imaging process, called beamforming, consists essentially of computing delay and apodization profiles. We have previously devised an approximation of the delay calculation stage, which dramatically reduces hardware complexity. Unfortunately, this approximation introduces an intrinsic degree of inaccuracy that can be characterized as added image noise. In this paper, we identify an efficient approximated approach to the calculation of apodization profiles, that additionally minimizes (-76%) the error introduced during delay calculation. Together, these two techniques enable an efficient computation of 3d ultrasound images.

关键词： delays Probes Transducers Imaging Three-dimensional displays Ultrasonic imaging Hospitals

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A floating high-voltage level-shifter with high area efficiency for biomedical implants

A floating high-voltage level-shifter with high area efficie...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Michael Haas Maurits Ortmanns Institute of Microelectronics University of Ulm Ulm Germany

ISBN: (纸本)9781509004942

A major problem in State-of-the-Art digital, floating level-shifters is, that they either require a large area when employing positive feedback, or lack accuracy with respect to the floating digital supply, if an open-loop solution is used. In order to reach accurate, floating, digital supply levels, while using the area efficient, static level-shifter topology, a control-loop for the reference current is introduced. Thereby process, temperature and time related variations are compensated and the adaptive reference can be distributed to an arbitrarily large array of level-shifters. The whole architecture has been simulated, layouted and manufactured in a standard 0.18 μm HV CMOS process. Simulation results show, that the design is capable of shifting digital signals from 0/3V to a floating 6/9V and -6/-9V domain with a delay of 250 ns and 150 ns respectively. By reducing the amount of high voltage transistors and utilizing low voltage diodes in the floating voltage domain, an area of only 65 μm × 33 μm per level-shifter can be realized. This is especially advantageous for the intended application in a multichannel neural stimulator, where many level-shifters are needed to switch the dedicated functions in the floating high voltage domains. The required bias current control-loop has a simulated power consumption of only 94 μW and requires an area of 137 μm × 97 μm.

关键词： Transistors Inverters Electric potential MOS devices Power demand Threshold voltage Switches

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conference Proceedings - 9th conference on ph. d. research in microelectronics and electronics, PRIME 2013

Conference Proceedings - 9th Conference on Ph. D. Research i...

引用

9th conference on ph. d. research in microelectronics and electronics, PRIME 2013

ISBN: (纸本)9781467345804

The proceedings contain 85 papers. The topics discussed include: comparison of high-voltage linear transmitter topologies for ultrasound CMUT applications;phase noise comparative analysis of LC oscillators in 28-nm CMOS through the impulse sensitivity function;graph coverage: an FPGA-targeted implementation;design-space exploration of an eFPGA soft-core based on multi-stages switching networks;direct digital frequency synthesizers implemented on high end FPGA devices;variable-step 12-bit AdC based on counter ramp recycling architecture suitable for CMOS imagers with column-parallel readout;an automatic calibration circuit for 12-bits single-ramp A-to-d converter in LHC environments;investigation of two-point modulation to increase the GFSK data rate of PLL-based wireless transceivers of wireless sensor nodes;and transient analysis applying S-parameters as operators.

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Communication energy constrained spare core on NoC 11

Communication energy constrained spare core on NoC

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11th conference on ph.d. research in microelectronics and electronics, PRIME 2015

作者： Kumar, B. Naresh Sharma, dheeraj Dept. of Electronics and Communication Engineering NIT Goa India

ISBN: (纸本)9781479982295

In Multi-processor System on-chip, each processor produce and consumes high data. Transporting of data is a crucial role in MPSOC, Therefore Network on Chip (NoC) preferred as a communication medium, because good communication performance and fast operating. While considering NoC Architectural some temporary, permanent faults occur in the core. This paper propose the placement of spare core and its communication energy constraints, we investigated energy metrics in place of spare core and finally saving communication energy leads to previous algorithms. © 2015 IEEE.

关键词： Network-on-chip

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An ultra-low power, 2mA Iout buck converter optimized for <50mV ripple at a load cap of only 27nF 11

An ultra-low power, 2mA Iout buck converter optimized for <5...

引用

11th conference on ph.d. research in microelectronics and electronics, PRIME 2015

作者： Santoro, F. Schmitt-Landsiedel, d. Gibson, N. Kuhn, R. Tost, T. Brederlow, R. Institute for Technical Electronics Technical University of Munich Munich Germany Texas Instruments Deutschland Freising Germany

ISBN: (纸本)9781479982295

A novel, simple dC-dC concept for low-power applications is presented. We propose a predictive peak-current mode controller in discontinuous conduction mode (dCM). The design is able to operate with a minimized output capacitor of only 27nF. Measurements shows low ripple voltage even at maximum load current steps and excellent transient response at a good dC control of Vout. © 2015 IEEE.

关键词： Energy efficiency

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A configurable sawtooth based PWM generator with 2 ns on-time for >50 MHz dCdC converters 11

A configurable sawtooth based PWM generator with 2 ns on-tim...

引用

11th conference on ph.d. research in microelectronics and electronics, PRIME 2015

作者： Wittmann, Juergen Wicht, Bernhard Robert Bosch Center for Power Electronics Reutlingen University Reutlingen Germany

ISBN: (纸本)9781479982295

Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. The maximum switching frequency and the maximum conversion ratio are limited by the duty cycle of a PWM signal. In dCdC converters, a sawtooth generator is the fundamental circuit block to generate the PWM signal. The presented PWM generator is based on two parallel, fully interleaved PWM generator stages, each containing an integrator based sawtooth generator and two 3-stage highspeed comparators. A digital multiplexing of the PWM signals of each stage eliminates the dependency of the minimum on-time on the large reset times of the sawtooth ramps. A separation of the references of the PWM comparators in both stage allows to configure the PWM generator for a dCdC converter operating in fixed frequency or in constant on-time mode, which requires an operation in a wide frequency range. The PWM generator was fabricated in an 180 nm HV BiCMOS technology, as part of a dCdC converter. Measurements confirm minimum possible on-time pulses as short as 2 ns and thus allows switching frequencies of dCdC converters of >50 MHz at small duty cycle of © 2015 IEEE.

关键词： Comparators (optical)

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Electromagnetic Evaluation of Class-d Switching Schemes 11

Electromagnetic Evaluation of Class-D Switching Schemes

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2015 11th conference on phd Res in Microelect & Elect PRIME

作者： Karaca, Timucin deutschmann, Bernd Graz Univ Technol Inst Elect Graz Austria

ISBN: (纸本)9781479982295

Class-d audio amplifiers may significantly contribute to the electromagnetic emissions of electronic devices. This work deals with the electromagnetic emissions created by Class-d amplifier output stages. Output stage switching schemes of traditional and filterless Class-d amplifiers are analyzed concerning their ability to create electromagnetic disturbances. Three different switching schemes are compared, namely Class-Ad, Class-Bd, and Ternary switching. Finally, commercially available Class-d amplifier ICs are measured and compared using an electromagnetic compatibility measurement setup according to IEC61967-4-A1.

关键词： Power amplifiers

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