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检索条件"任意字段=Conference on Ph.D Research in Microelectronics and Electronics"

共 836 条记录，以下是61-70 订阅

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Blockchain-based implementation of Tradable Green Certificates

Blockchain-based implementation of Tradable Green Certificat...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Antonio J. Cabrera-Gutierrez Encarnación Castillo Antonio Escobar-Molero diego P. Morales Luis Parrilla R&D Funding Infineon Technologies AG Munich Germany Dept. of Electronics and Computer Technology University of Granada Granada Spain

Blockchain networks, given that they are not based on power-hungry proof-of-work methods, can be used in smart grid applications, in particular in the tradable green certificates use case. Thanks to the Blockchain and the smart contracts implemented, certificates can be tracked and exchanged between entities without the intervention of third parties, as well as keeping an immutable and reliable record of these certificates. This work proposes a hardware implementation of a green certificate trading system based on Blockchain, in which prosumers use hardware secure elements to implement the cryptographic tools used to interact with the Blockchain. Smart contracts help to automate these processes, deleting intermediaries, saving costs and avoiding bureaucracy.

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A Sub-100 mV AC/dC Converter with Impedance Matching for Magnetic Field Energy Harvesting

A Sub-100 mV AC/DC Converter with Impedance Matching for Mag...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Harald dillersberger douglas Tham Bernd deutschmann Institute of Electronics Graz University of Technology Graz Austria Matrix Industries Menlo Park CA USA

Energy harvesting from ambient sources can be used to supply low-power devices in remote areas or where it is costly to replace batteries. Other than light, temperature gradients, vibrations and radio frequency electromagnetic radiation, it is also possible to harness ambient energy from an alternating electric or magnetic field. Magnetic field energy harvesting (MFEH) is possible with inductors near AC current-carrying power lines. This paper presents a novel converter for boosting the low-voltage AC output of small magnetic field energy harvesters to power standard electronic circuits. The design in a 180 nm CMOS process is illustrated and efficiency and system level power measurements are performed to proof the concept.

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Noise Figure Analysis in Current Mode direct Conversion Receivers

Noise Figure Analysis in Current Mode Direct Conversion Rece...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Alessio Luongo Stefano d’Amico Maurizio Inversi Angelo Malvasi Dept. of Engineering for Innovation University of Salento via per Monteroni Lecce Italy Cortus Srl via Tufi 4 Lecce Monteroni Italy

The purpose of this paper is to face the problem of the noise Figure calculation in case of direct conversion current mode receiver (RX). In the considered receivers architecture the down-conversion operation is done by mixing the input current signal by a square waveform oscillating at a frequency equal to the carrier of the RF signal. Moreover, the presence of the harmonics in the square waveform mixing signal produces noise folding which worsen the noise Figure of the RX. A possible solution has been proposed and it consists to introduce a band-pass filtering after the low-noise transconductance amplifier. After a system level analysis of the problem a circuit example in 65nm CMOS technology is proposed. Calculated and simulated results for the noise Figure match very well demonstrating the correctness of the proposed approach.

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Asynchronous vs Synchronous SAR AdCs – Performance Beyond Nominal Speed

Asynchronous vs Synchronous SAR ADCs – Performance Beyond N...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Hamid Karrari Pietro Andreani Siyu Tan Department of Electrical and Information Technology Lund University Lund Sweden

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

This paper presents a comparison between a Itl-bit asynchronous SAR (ASAR) AdC and a 10-bit synchronous SAR (SSAR) AdC, both designed and simulated in a 22-nm FdSOI CMOS process. To further support the simulation results, the ASAR AdC has also been fabricated and measurements are pre-sented. As opposed to the abrupt SNdR collapse in the SSAR AdC, the SNdR of the ASAR AdC shows a more graceful deg-radation as the sampling frequency is increased beyond the highest nominal. At the same time, the ASAR AdC consumes approximately 20% less power than the SSAR AdC.

关键词： Atmospheric measurements Simulation Silicon-on-insulator CMOS process Particle measurements microelectronics

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Improving Performance of InGaP/GaAs HBT Arrays by means of Temperature-dependent Base Ballasting Resistors

Improving Performance of InGaP/GaAs HBT Arrays by means of T...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Ciro Scognamillo Antonio Pio Catalano Vincenzo d’Alessandro Peter J. Zampardi Kerry Burger Department of Electrical Engineering and Information Technology University Federico II Naples Italy Qorvo Inc. Newbury Park CA USA Qorvo Inc. Summerfield NC USA

Base ballasting resistors (BBRs) are commonly adopted to minimize electrothermal(ET) effects in arrays of bipolar transistors for power amplifier (PA) applications. In this paper, innovative BBRs with temperature-dependent resistivity are proposed in order to improve the trade-off between safe-operating area (SOA) and radiofrequency (RF) performances. As a simple case-study, a three-cell heterojunction bipolar transistor (HBT) fabricated by Qorvo is considered and circuital ET simulations are performed in AdS. Results of the comparison between the proposed strategy and the traditional one are discussed, thus providing useful insights into the advantages of temperature-dependent BBRs.

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Assessment of Recurrent Spiking Neural Networks on Neuromorphic Accelerators for Naturalistic Texture Classification

Assessment of Recurrent Spiking Neural Networks on Neuromorp...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Haydar Al Haj Ali Ali dabbous Ali Ibrahim Maurizio Valle Department of Electrical Electronic Telecommunication Engineering and Naval Architecture DITEN University of Genoa Genova Italy Department of Electrical and Electronics Engineering Lebanese International University (LIU) Beirut Lebanon

This paper presents the implementation of a Recur-rent Spiking Neural Network (RSNN) using surrogate gradient descent for naturalistic textures classification. The implementation choices for the RSNN are limited to hardware-friendly models since it is intended to be integrated into an electronic skin system. Hence, a comparison between the von-Neumman and neuromorphic computing approaches has been assessed in terms of hardware efficiency. The energy consumption per inference of the proposed model is estimated using the KerasSpiking tool built-in NengodL framework, on three different devices namely: GPU, Intel Loihi, and SpiNNaker. The obtained results indicate that the aforementioned neuromorphic devices achieve several orders of magnitude gains in energy over von-Neumman hardware. Moreover, the proposed RSNN model overcomes similar state-of-the-art solutions in terms of classification accuracy and hardware complexity making it a promising candidate for embedded electronic skin applications.

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An Integrated Multi-Order digital Control Unit for Maximum Length Sequence Circulant Matrix Generation 17

An Integrated Multi-Order Digital Control Unit for Maximum L...

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17th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Radogna, Antonio Vincenzo Capone, Simonetta Francioso, Luca Siciliano, Pietro Aleardo d'Amico, Stefano Natl Res Council CNR Inst Microelect & Microsyst IMM Lecce Italy Univ Salento Dept Engn Innovat Lecce Italy

ISBN: (纸本)9781665467001

In this work an integrated multi-order digital control unit (dCU), for the generation of a maximum length sequence (MLS) circulant matrix, is proposed. The system provides the binary MLS through serial output. It has the possibility to select the M order of the MLS according to the application. When compared to conventional implementations, the proposed system does not rely on read-only memory (ROM) data storage since the circulant sequences are generated on the fly during the circuit's operation. This permits to implement multiple order circulant matrices, while mantaining a reduced area occupation. Moreover, the proposed circuit can be implemented with digital standard cell synthesis, avoiding dedicated digital flows for memories. The dCU has been verified with behavioral simulation using a 2MHz clock frequency and has been realized in CMOS 28nm Fd-SOI technology with a total area occupation of 45 mu m x 45 mu m. From the RTL synthesis, a total power consumption of 8.2 mu W is obtained.

关键词： MLS PRBS circulant matrix LFSR CMOS digital circuits

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A Reconfigurable dual-Mode Integrated CMOS Laser diode driver for iToF/dToF Based 3d Sensing

A Reconfigurable Dual-Mode Integrated CMOS Laser Diode Drive...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Ruixuan Yang Yuye Yang Shuaizhe Ma Bing Zhang dan Li Faculty of Electronic and Information Engineering of Xi’an Jiaotong University Xi’an China

A reconfigurable dual-mode laser diode driver has been designed in a standard 180-nm CMOS process for iToF(indirect Time-of-Flight) and dToF (direct Time-of-Flight) based 3d sensing. A reconfigurable and power-efficient driver output stage is proposed, which enables both iToF and dToF operation. In iToF mode, the driver produces a maximum output current of 4.2 A with 50% duty cycle. A ringing suppression circuit is also introduced to reduce the undesired ringing at the end of each pulse. In dToF mode, the driver generates a 3.8-A peak pulse with a minimum pulse width of 737 ps. The output efficiency is 87% in iToF mode and 92% in dToF mode with 4-A output current. To the authors’ knowledge, this is the first reconfigurable dual-mode laser diode driver compatible with both iToF and dToF LidAR systems.

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Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives

Hardware architecture for CRYSTALS-Kyber post-quantum crypto...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Alessandra dolmeta Maurizio Martina Guido Masera Department of Electronics and Telecommunications Politecnico di Torino Torino Italy

Once powerful enough quantum computers become feasible, many of the regularly used cryptosystems will be completely useless. Thus, designing quantum-safe cryptosystems to replace current algorithms is more crucial than ever. This paper presents the hardware implementation of one of the fundamental building blocks of all post-quantum cryptographic (PQC) algorithms, which are PQC-primitives, having NIST-PQC-finalists CRYSTALS-Kyber algorithm as a target. This work analyzes Keccak sponge function and the four SHA-3 algorithms used in CRYSTALS-Kyber, realizing the correct processing and handling of input information and integrating the four standards into one implementation for Kyber-III level of security. The synthesis results are provided for 65-nm technology, while Artix7 XC7A75-3 is chosen as the implementation platform. The efficiency and the performance of the proposed architecture are compared in terms of area, frequency, clock cycles, and efficiency with the state-of-the-art.

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Analysis and design of High-Speed, Linear and Fullscale Input Swing Voltage to Time Converters

Analysis and Design of High-Speed, Linear and Fullscale Inpu...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Shivani Ankesh Jain Department of Electrical Engineering Indian Institute of Technology Delhi India

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

The output performance of time-based analog to digital converters (AdCs) realized using voltage to time convert-ers (VTCs) is limited due to the nonlinear behaviour of VTC. This work attempts to analyze existing VTC architectures to understand the limitations of VTC design. It further proposes a novel VTC architecture that achieves full-scale input swing and operates at 1 GS/s. The proposed VTC architecture is designed using CMOS 65 nm process and post-layout simulation results are presented to show its efficacy. It achieves 7.3 ENOB while consuming 0.2 mW power. It has a figure of merit of 1.3 fJ/cs-step and an output range of 410 ps.

关键词： Simulation Linearity Voltage microelectronics Analog-digital conversion

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