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检索条件"任意字段=Conference on Ph.D Research in Microelectronics and Electronics"

共 834 条记录，以下是71-80 订阅

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Impact of Input Encoding and AdC Resolution on Matrix-Vector Multiplication Accuracy

Impact of Input Encoding and ADC Resolution on Matrix-Vector...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Riccardo Vignali Gianluca Ricotti Riccardo Zurla Marco Pasotti Alessandro Cabrini Department of Electrical Computer and Biomedical Engineering University of Pavia Italy ST Microelectronics Agrate Brianza Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

Analog In-Memory Computing based on Non-Volatile Memories is a promising candidate to reduce latency and power consumption of neural network inference in edge-computing applications. This kind of computational accelerators allows both storing weights and performing in-situ analog computation inside the array. This analysis evaluates the impact that input encoding schemes could have on the accuracy of Matrix-Vector Multiplication (MVM), depending on AdC resolution. Two commonly used encoding technique, Pulse Width Modulation and Bit-Serial, are assessed in term of computation time, system resolution and average MVM error.

关键词： Accuracy Power demand Nonvolatile memory Neural networks Noise Pulse width modulation In-memory computing

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Enhancing Electrical Ruggedness in double-Sided Cooled Power Modules

Enhancing Electrical Ruggedness in Double-Sided Cooled Power...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Ciro Scognamillo Antonio Pio Catalano Lorenzo Codecasa Alberto Castellazzi Vincenzo d'Alessandro Department of Electrical Engineering and Information Technology University Federico II Naples Italy Department of Electronics Information and Bioengineering Politecnico di Milano Milan Italy Solid-State Power Processing (SP2) Lab Faculty of Engineering Kyoto University of Advanced Science Kyoto Japan

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

This paper explores the electrical ruggedness of double-sided cooled (dSC) power modules by focusing on the influence of the spacing between interfacing substrates on the voltage endurance of the assembly. For the first time, it is suggested to fill the silicone gel surrounding the dies with barium titanate (BaTiO 3 ) in this technology. The analysis relies on detailed numerical simulations performed with COMSOL Multiphysics. Results confirm the beneficial pushout effect dictated by a reduced spacing. Additionally, it is found that integrating BaTiO 3 increases the critical voltages that the module can withstand before the breakdown onset.

关键词： Barium Multichip modules Focusing Numerical simulation microelectronics Finite element analysis Titanium compounds

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Ultra-Low Power Heart Rate Estimation with VCO-based AdCs

Ultra-Low Power Heart Rate Estimation with VCO-based ADCs

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ph.d. research in microelectronics and electronics (PRIME)

作者： Leidy Mabel Alvero-Gonzalez Carlos Perez Natalia Martinez Ana Mejon Eric Gutierrez Electronics Technology Carlos III University of Madrid Madrid Spain History Geography and Communication University of Burgos Burgos Spain Communication and Media Studies Carlos III University of Madrid Madrid Spain

A system and circuit approach to perform ultra-low power heart estimation is proposed towards biomedical wearables. A voltage controlled oscillator based analog-to-digital converter (VCO-based AdC) implemented with a ring oscillator is used for the digitization of a blood volume pulse (BVP) signal. The digital output data then feed digital logic circuits that perform simple operations to achieve an accurate measurement of the heart rate. The resulting circuit is mostly scalable, consumes nWs and the accuracy performance is completely independent from the VCO non linearity. A proposal has been designed using a 65 nm CMOS node leading to a power consumption of only 108 nW and a heart rate error less than 1 bpm.

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Area-Efficient and Wideband Input Stages for SiGe BiCMOS G-Band LNAs

Area-Efficient and Wideband Input Stages for SiGe BiCMOS G-B...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Alvaro Urain david del Rio Roc Berenguer TECNUN - Universidad de Navarra Spain CEIT - Basque Research and Technology Alliance (BRTA) Spain

Simultaneous wideband input matching and gain performance while maintaining low core area is one of the big challenges of mmW amplifier design. In this work, the stacked common base (stacked CB) configuration is proposed for the input stage of an amplifier to achieve a good compromise between gain, input matching and area. The stacked CB topology is compared with the cascode and simple CB configurations to prove its validity. Finally, two G-Band amplifiers are designed with different input stage topologies: cascode and stacked CB. Both show very small core areas (0.066 and 0.085 mm 2 respectively) while maintaining gains of 22.8 and 22.5 dB, NF of 9.4 and 9.9 dB and GBW product of 317 and 346 GHz respectively that are comparable to the SoA. The stacked CB version shows a wideband input bandwidth of 76 GHz $(S11 < -10$ dB), making it a suitable choice for area-efficient and broadband input stages.

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A 40V Robust Leakage Current based Start-Up Circuit

A 40V Robust Leakage Current based Start-Up Circuit

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ph.d. research in microelectronics and electronics (PRIME)

作者： Lara devoti Giovanni Sicurella Alessandro Nicolosi Manuela La Rosa Politecnico di Milano Milano Italy STMicroelectronics Catania Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

In this paper we present a new startup circuit designed and implemented to achieve optimized current consumption features over a wide supply voltage range. This makes the architecture suitable for high voltage industrial and automotive applications. The circuital solution exploits leakage current of a MOS transistor in off state. The validation of the architecture has been performed by demonstrating the unicity of the stability point and the effectiveness in reaching it. The robustness of the proposed solution is ensured by the balancing of leakage currents of devices of the same type. The proposed circuit is implemented in BCd 110 nm technology node, and it is based on 40V dMOS transistors.

关键词： Performance evaluation MOSFET Voltage Mathematical models Stability analysis Robustness microelectronics

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A 270 fJ/op 5.8 GHz MOS Current Mode Logic d-Latch for High-Speed Application

A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Abdullah Alshehri Abdullah Alqarni Kuilian Yang Hossein Fariborzi Computer Electrical and Mathematical Science & Engineering Division King Abdullah University of Science and Technology (KAUST) Thuwal Saudi Arabia Computer Electrical and Mathematical Science & Engineering Division Electronics and Communication Engineering Umm Al-Qura University Al-Leith Saudi Arabia

In this paper, we present the design of a new low-power, high-performance MOS Current Mode Logic (MCML) d-Latch. The proposed design consists of cross-coupled transistors which dynamically control the load resistance and eliminate static power dissipation. The performance of the design was improved by reducing the threshold voltage of the input transistors at the critical phase to switch them ON faster using the clocked-driven forward body biasing technique. The proposed design achieves an energy improvement of 54% and 49% and a performance improvement of 20% and 43% compared to the Folded and Folded (dTMOS) d-Latches, respectively. The designs were simulated on Cadence Virtuoso AdE tool using 40 nm technology TSMC PdK. Moreover, the proposed design provides higher output voltage swing and is less sensitive to the change of load capacitance compared to the other designs.

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A Sustainable Printed Chitosan-Based Sensor for Acetone detection

A Sustainable Printed Chitosan-Based Sensor for Acetone Dete...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Johanna Zikulnig Sabine Lengger Lukas Rauter Sandro Carrara Jürgen Kosel Sensor Systems Silicon Austria Labs GmbH Villach Austria EPFL STI IEM ICLAB École Polytechnique Fédérale de Lausanne Neuchâtel Switzerland

Biomedical sensing applications, including breath analysis, contribute to increasing the amount of electronic waste, as the sensors are frequently disposed, due to hygienic considerations. Consequently, the development of sustainable sensor solutions is crucial. Here, a Chitosan-based sensor proposed for the utilization in biomedical applications is presented. The sensor is fabricated on a bio-sourced and biocompatible thermoplastic polyurethane substrate, and its response to Acetone vapor is studied. The use of Chitosan, a natural biopolymer, together with additive manufacturing technologies make this sensor sustainable, while the use of biocompatible materials makes it well-suited for biomedical applications. The sensor shows a good linearity in the range between ambient Acetone concentrations of 0 -73 ppm with relative changes of 0.42% per ppm and 2.75% per ppm at ambient humidities of $50 \pm 5$%rH and $80\pm 5$%rH, respectively.

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Enhancing Performance of Ultra-Low Voltage Body-driven Comparators Through Clocked Supply Voltage

Enhancing Performance of Ultra-Low Voltage Body-Driven Compa...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Riccardo della Sala Cristian Bocciarelli Valerio Spinogatti Francesco Centurelli Alessandro Trifiletti Sapienza University Of Rome Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

In this work, a novel technique to feed body-driven ultra-low voltage (ULV) comparators is investigated to enhance performance in terms of noise and offset. The technique, which consists in clocking the supply voltage of the latch devices, causes the output common mode voltage to experience a positive step at the beginning of the evaluation phase. As a result, the preamplification gain is enhanced because the output nodes are discharged for a longer time before the latch turns on. The proposed approach is validated by applying it to an ULV comparator topology proposed in a previous work. Post-layout simulation results on a 130nm node demonstrate that input-referred noise and offset improve approximately 20% and 15%, respectively, while the energy-delay product of the comparator EdP remains essentially unchanged.

关键词： Performance evaluation Latches Simulation Noise Voltage Topology microelectronics

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design of a Hardware-Efficient Floating-Point Multiplier with dynamic Segmentation

Design of a Hardware-Efficient Floating-Point Multiplier wit...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Luca Tegazzini Gennaro di Meo davide de Caro Antonio G. M. Strollo DIETI- Univ. di Napoli Federico II Napoli Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

In this paper, we present a novel low-power floating-point multiplier design that leverages dynamic segmentation to enhance efficiency. Our approach approximates the mantissa product through a simple addition of dynamically extracted input segments, supplemented by an additional correction term implemented through a small, hardwired lookup table. Compared to previous proposals, our FPM shows optimal results in terms of the power-accuracy trade-off, with power savings exceeding 85% compared to an exact implementation. The proposed multiplier offers remarkable performance in image processing applications, with Structural Similarity Index (SSIM) values approaching 1 and Peak Signal-to-Noise Ratio (PSNR) reaching up to 66dB.

关键词： Measurement Image segmentation PSNR Accuracy Table lookup microelectronics Proposals

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Compact SPAd Pixels with Analogue Counter for Ultraviolet Imaging

Compact SPAD Pixels with Analogue Counter for Ultraviolet Im...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Soumya Shatakshi Panda Qiushuang Zhang Bhaskar Choubey Chair of Analogue Circuits and Image Sensors University of Siegen Siegen Germany

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

A compact actively quenched and recharged n+/p-well SPAd pixel circuit for ultraviolet (UV) imaging is being reported in this paper. This circuit is designed using a high volt-age CMOS process. The pixel includes a 10-bit analogue counter utilizing only five transistors for photon counting applications. The hold -off time of the pixel can be tuned between 2.28 ns to 67 ns using an in-pixel voltage-tuneable delay circuit, thereby, minimizing the possibility of after-pulsing effects. Simulation results show a fast quenching and recharge time of 1.32 ns and 0.96 ns, respectively. The pixel occupies an overall area of 27 µm x 31 µm and has a fill factor of 9.5%.

关键词： Image resolution Fill factor (solar cell) Simulation Imaging Linearity microelectronics delays

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