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Historical reconstruction dataset of hourly expected wind generation based on dynamically downscaled atmospheric reanalysis for assessing spatio-temporal impact of on-shore wind in Japan

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Big Earth data 2024年第4期8卷 732-754页

作者： Yu Fujimoto Masamichi Ohba Yujiro Tanno daisuke Nohara Yuki Kanno Akihisa Kaneko Yasuhiro Hayashi Yuki Itoda Wataru Wayamad Advanced Collaborative Research Organization for Smart Society Waseda UniversityTokyoJapan Sustainable System Research Laboratory Central Research Institute of Electric Power IndustryAbikoChibaJapan Department of Advanced Science and Engineering Waseda UniversityTokyoJapan Power System Engineering Department Tohoku Electric Power Network Co.Inc.SendaiMiyagiJapan

Wind power is crucial for achieving carbon neutrality,but its output can vary due to local wind *** spatio-temporal behavior of wind power generation connected to the power grid can have a significant impact on system *** assess this impact,the use of long-term reanalysis results of wind data based on a numerical weather prediction(NWP)model is considered ***,in Japan,the behavior of on-shore wind power generation is influenced by diverse topographical and meteorological features(TMFs)of the installation site,making it challenging to assess possible operational impacts based solely on power curve-based estimates using a popular conversion *** this study,a nonparametric machine learning-based post-processing model that learns the statistical relationship between the TMFs at the target location and the actual wind farm(WF)output was developed to represent the expected per-unit output at each *** on historical reconstruction results and using this post-processing model to reproduce the real-world WF output behavior created a set of expected wind power generation *** dataset includes hourly long term(1958-2012)wind power generation profiles expected under the WF installation assumptions at various on-shore locations in Japan with a 5 km spatial resolution and is expected to contribute to an accurate understanding of the impact of spatio-temporal wind power *** dataset is publicly accessible at https://***/10.5281/zenodo.11496867(Fujimotoet al.,2024).

关键词： On-shore wind power numerical weather prediction machine learning post-processing dataset

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Hardware Modelling and Testing of a Rotating Neuron Reservoir

Hardware Modelling and Testing of a Rotating Neuron Reservoi...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Antonia Pavlidou Mohammed Waqas Mughal Meraj Ahmad Hadi Heidari Microelectronics Lab (meLAB) James Watt School of Engineering Glasgow United Kingdom

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

Rotating neural networks (RNRs) have been proven very efficient in executing in-memory computing tasks, while their potential to be implemented in full hardware massively reduces their power consumption. This paper reports the hardware modelling and simulations of an RNR using Cadence virtuoso tools, demonstrating the performance using the Mackey–Glass (MG) chaotic mathematical series for prediction. The readout layer calculations were performed using MATLAB, and the results were compared with the respective full MATLAB ideal algorithm. The Cadence/MATLAB hybrid algorithm has exhibited an NRMSE=0.042 for a reservoir size of 3 neurons, compared to the ideal MATLAB model, which gave a result of NRMSE=0.0267 for the same number of neurons.

关键词： Training Computational modeling Neurons Predictive models Reservoirs Prediction algorithms Mathematical models

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EROdE: Error Resilient Object detEction by Recovering Bounding Box and Class Information

ERODE: Error Resilient Object DetEction by Recovering Boundi...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Emanuele Valpreda Giuseppe Palumbo Michele Caon Guido Masera Maurizio Martina Department of Electronics and Telecommunications Politecnico di Torino Italy ST Microelectronics Italy

Fault resilience in computer vision algorithms is paramount in critical applications such as autonomous driving or surveillance. Convolutional neural networks (CNNs) are usually used in these tasks to identify objects of interest, which are passed to other decisional algorithms and used to take specific actions. However, incorrect detections due to computation errors could pose a safety risk. In this work, we present EROdE (Error Resilient Object detEction), a framework that can be paired with a CNN to filter the detections by identifying possible errors and restoring the correct predictions, improving the fault-resilience of the system. The proposed framework leverages the temporal correlation among consecutive images and CNN outputs, using motion estimation and tracking techniques to infer whether computation errors have occurred and, in that case, produce a new set of outputs. In order to evaluate the performance, precision and recall of the CNN with and without EROdE support have been computed and compared using the MOT17dET dataset, and Efficientdet dO quantized to 16-bit, with errors injected in the activations computed during the inference. The experimental results show significantly reduced task accuracy degradation induced by bit-flips, proving that EROdE can increase the system’s fault resilience.

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Enhancement-mode p-GaN Comparators for power applications

Enhancement-mode p-GaN Comparators for power applications

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ph.d. research in microelectronics and electronics (PRIME)

作者： Nataly Pozo Luis-Miguel Prócel Lionel Trojman Instituto de Micro y Nanoelectrónica-IMNE Universidad San Francisco de Quito Quito Ecuador Laboratoire d’Informatique Signal et Image Électronique et Télécommunication-LISITE Isep Paris France

This paper presents the design of three new comparators circuits for power applications using Enhancement-mode p-GaN HEMT Process design Kit (PdK) developed by IMEC. The design challenge in this technology is the lack of P-type devices, therefore diode-connected structures with N-type devices are introduced as pull-up devices. Comparators are monolithicaly integrated with 200V/10A power p-GaN HEMTs. The output voltage of the comparators is set to 6V to turn-on the power device suitably. To verify the performance of the circuits, lMHz of input signal frequency is selected. Relevant parameters such as rising, falling and propagation delay times, together with the power-delay product are discussed. For rated output voltage and frequency, the lower rise/fall/propagation delay times achieved are 0.8310.8911.14 ns. Transistor-level simulations and proof of concept of each proposed structure are carried out considering temperature and frequency variation.

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A Novel Mixed-Signal Silicon photomultiplier with Analog-domain Cross-Correlation Computation for LidAR Applications 17

A Novel Mixed-Signal Silicon Photomultiplier with Analog-Dom...

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17th conference on ph.d research in microelectronics and electronics (PRIME)

作者： Morciano, Arianna Gandola, Massimo d'Amico, Stefano Perenzoni, Matteo Fdn Bruno Kessler Sensors & Devices Povo Tn Italy Univ Salento Dept Innovat Engn Lecce Italy Fdn Bruno Kessler Povo Tn Italy Sony Europe Technol Dev Ctr Trento Italy

ISBN: (纸本)9781665467001

Light detection and Ranging (LidAR) is a widespread technique for distance measurements used in several applications. In this work, a novel Mixed-Signal Silicon photomultiplier (msSiPM) with analog-domain cross-correlation computation for LidAR applications is presented. Cross-correlation technique is commonly implemented at the end of the LidAR system signal chain to estimate the Time-of-Flight (ToF) and to calculate the measured distance. In this work, an innovative way of performing an approximated cross-correlation inside the detector frontend is presented and simulated. In particular, the typical impulse response of an analog-SiPM (aSiPM) with a specific dead-time is replaced by a custom impulse response by means of a microcell-level Pulse Shaper stage. In this way, it is possible to tune the pulse to approximate the time-reversed shape of the laser envelope and to perform an analog cross-correlation. Simulations have been carried out in MATLAB software: by using an msSiPM instead of an aSiPM, an advantage in terms of Signal-to-Noise Ratio (SNR) of 6 dB and of Signal-to-Background Ratio (SBR) of about 23 dB is obtained.

关键词： LidAR (Light detection and Ranging) SPAd (Single photon Avalanche diode) SiPM (Silicon photomultiplier) SNR (Signal-to-Noise Ratio) SBR (Signal-to-Background Ratio) cross-correlation

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Monte Carlo simulations of Fully depleted CMOS pixel sensors for radiation detection applications

Monte Carlo simulations of Fully Depleted CMOS pixel sensors...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Chiara Ferrero Coralie Neubüser Lucio Pancheri Angelo Rivetti Dep. of Electronics Engineering Politecnico di Torino INFN -Sezione di Torino Torino Italy INFN Trento Trento Institute for Fundamental Physics and Applications Trento Italy Dep. of Industrial Engineering TIPFA-INFN Trento University of Trento Trento Italy Dep. of Physics INFN -Sezione di Torino University of Torino Torino Italy

The ARCAdIA (Advanced Readout CMOS Architectures with depleted Integrated sensor Arrays) collaboration has developed $25 \mu m$ pitch Fully depleted Monolithic Active Pixel Sensors (MAPS) based on a modified 110 nm CMOS process in collaboration with LFoundry. This work illustrates a set of simulations performed on this detector technology, with the aim of investigating its capabilities for radiation detection applications. Three-dimensional Technology Computer Aided design (TCAd) simulations have been performed in order to extract the electric field and electrostatic potential maps suitable to execute Monte Carlo simulations, providing high statistics of particle-sensor interaction in a reasonable computing time. The simulation flow will be described in detail and the main results will be pointed out.

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Integrated GaN digital soft start-up for switching power converters

Integrated GaN digital soft start-up for switching power con...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Katia Samperi Nunzio Spina Salvatore Pennisi Giuseppe Palmisano DIEEI University of Catania Catania Italy R & D ADG STMicroelectronics Catania Italy

This paper presents an integrated soft start-up circuit implemented in a $0.5-\mu m$ GaN on Si technology suitable for on-chip integration in power applications. The proposed approach avoids the use of large on-chip or external capacitors to overcome the problem of voltage overshoot and inrush current at start up in switching power converters. It could be also adapted to the specific application by choosing the number of Flip Flops, or, for large start-up periods, using a counter, and setting the desired start-up signal duty cycle. Moreover, an optimized Flip Flop circuit topology has been proposed to reduce area occupation. The circuit working principle and the design challenges in GaN technology are discussed together with simulations. The circuit has been designed by considering worst-case conditions. A test buffer has been also included to drive the high external load capacitance of the readout device. Measured waveforms are reported that demonstrate the effective circuit operation and suitability for all-GaN integration.

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Empowering Smart Mobility with a Component-based data Acquisition System for Multi-sensor Readout

Empowering Smart Mobility with a Component-based Data Acquis...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Matteo Verzeroli Andrea Galliani Luca Ghislotti Luigi Gaioni Paolo Lazzaroni Valerio Re Dipartimento di Ingegneria e Scienze Applicate Università degli Studi di Bergamo Bergamo Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

This work presents a component-based data acqui-sition system for reading multi-sensor modules in the context of active mobility and light vehicles. Leveraging technologies coming from electric mobility in a light vehicle scenario means dealing with low power requirements and limited computational resources. To collect data simultaneously from different sensor platforms, an ad-hoc multi-process application has been developed for a single-board computer. This data acquisition module supports multi-protocol communication interfaces and it can aggregate data about the environment, the status of the vehicle and the user. Moreover, it can support the integration with an IoT communication infrastructure. A prototype of the system has been implemented to prove the feasibility of the architecture.

关键词： Aggregates data acquisition Prototypes Computer architecture data aggregation microelectronics Reliability

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A 4T GC-edRAM Bitcell with differential Readout Mechanism For High Performance Applications

A 4T GC-eDRAM Bitcell with Differential Readout Mechanism Fo...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Roman Golman Avinoam Segev Adam Teman EnICS Labs Faculty of Engineering Bar Ban University Ramat Gan Israel

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

Gain-cell embedded dRAM (GC-edRAM) is a dense, low power option for embedded memory implementation, supporting low supply voltages. However, due to its structure, the readout scheme is slow and requires a high precision external reference voltage to improve performance. In this work, we propose a novel bitcell featuring a differential readout mechanism for high frequency operation without the need for an external voltage supply. A 16 kbit memory macro was implemented in 65nm CMOS bulk technology offering up to 3x improvement in access time compared to standard GC-edRAM solutions and similar read time to SRAM bitcells, while providing up-to 30% reduction in bitcell area compared to standard SRAM solution.

关键词： Power demand Random access memory CMOS technology discharges (electric) Topology Sensors microelectronics

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Exploring Variable Latency dividers in Vector Hardware Accelerators

Exploring Variable Latency Dividers in Vector Hardware Accel...

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ph.d. research in microelectronics and electronics (PRIME)

作者： Marco Angioli Marcello Barbirotta Abdallah Cheikh Antonio Mastrandrea Mauro Olivieri Sapienza University of Rome Rome Italy

ISBN: (数字)9798350386301

ISBN: (纸本)9798350386318

Efficient hardware implementation of integer division remains one of the most significant challenges in the design of vector hardware accelerators, particularly in achieving a balance between performance and hardware overhead. This work uses the RISC-V Klessydra-T13 Vector Coprocessor Unit as a case study to explore the impact of variable latency division architectures for vector hardware accelerators. We analyze existing designs in the literature to identify the most effective approach, detailing the whole integration process with new instructions for supporting vector divisions in the RISC-V custom instruction set and optimizing the implementation for the target accelerator by exploiting hardware reuse. We also provide real-world computation kernels and Monte Carlo simulations to demonstrate how a variable latency divider can significantly improve the division time over traditional methods with negligible hardware overhead.

关键词： Monte Carlo methods Instruction sets Computer architecture Benchmark testing Vectors microelectronics Kernel

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