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检索条件"任意字段=Conference on PhD Research in Microelectronics and Electronics"

共 86 条记录，以下是21-30 订阅

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Implementation of a low power decimation filter in a 180 nm HV-CMOS technology for a neural recording front-end 16

Implementation of a low power decimation filter in a 180 nm ...

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2021 International conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2021 and 16th conference on phd research in microelectronics and electronics, PRIME 2021

作者： Sporer, Markus Graber, Nicolas Moll, Steffen Reich, Stefan Ortmanns, Maurits Institute of Microelectronics University of Ulm Albert-Einstein-Allee 43 Ulm Germany

ISBN: (纸本)9783800755899

The design of decimation filters for Delta Sigma Converters is a rarely discussed topic though these filters are necessary for ?S modulator ADCs. In this work, we present a low-power decimation filter for a neural recording front-end. We show the applied design criteria and compare different filter structures to find the most efficient implementation. The decimation filter has been implemented and simulated in a 180 nm HV-CMOS process. It achieves a low power consumption of 6.4 µW at a supply voltage of 1.2 V. The filter has a 13 bit output running at a sampling rate of 22 kHz and requires an area of 460 µm x 210 µm. The input signal’s SNDR degradation due to the filter is less than 2 dB. © VDE VERLAG GMBH.

关键词： CMOS integrated circuits

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A 2GS/s 10-bit time-interleaved capacitive DAC for self-interference-cancellation application 16

A 2GS/s 10-bit time-interleaved capacitive DAC for self-inte...

引用

作者： Eslami, Mazyar Abedinkhan Manstretta, Danilo Castello, Rinaldo Microelectronics Laboratory University of Pavia Pavia Italy

ISBN: (纸本)9783800755899

This article presents a 2-GS/s time-interleaved (TI) 10-bit capacitive digital-to-analog converter (CDAC) for self-interference-cancellation (SIC) application. It is also capable of working as a non-TI & stand-alone CDAC with 1-GS/S clock frequency. By taking advantage low parasitic capacitance and equivalent parasitic capacitance at bottom and top plate of MIM capacitor, the split-capacitor technique is used without significant degradation in the linearity. The special architecture of the designed layout also relieves the local and radial oxide gradient error. The CDAC is designed in 28nm CMOS technology. If the CDAC works in stand-alone mode with 1-GS/s clock frequency, followed by an additional anti-aliasing filter and the baseband input frequency equals 10.74 MHz, the ENOB, SFDR and THD at the output of the filter is equal to11.3-bit,76 dB and 76dB, respectively. © VDE VERLAG GMBH.

关键词： Digital to analog conversion

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Integrated hysteretic controlled regulating buck converter with capacitively coupled bootstrapping 16

Integrated hysteretic controlled regulating buck converter w...

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作者： Galea, Francarl Casha, Owen Grech, Ivan Gatt, Edward Micallef, Joseph Department of Microelectronics and Nanoelectronics University of Malta Malta

ISBN: (纸本)9783800755899

This paper presents the circuit design, layout implementation and simulations of an on-chip hysteretic regulating buck converter. All the high voltage transistors of the buck converter were implemented using 45 V NMOS thin gate oxide layer transistors and are operated by means of a capacitively coupled bootstrap circuit. The circuit was implemented using the XFAB CMOS 0.35 µm high voltage technology and all the circuit blocks were designed using analog electronic techniques, with the transistors operating in the sub-threshold region, in order to minimize power consumption. Simulations show that the control circuit of the hysteretic regulator consumes around 0.5 µW, and the proposed buck converter operates at a peak efficiency of 82%. The input voltage range of the regulator is from 1.5 V to 45 V and has a power range from 10 µW to 200 mW. The output regulated voltage is tunable via a feedback resistor and can be varied from 0.6 V to 40 V, with a dropout voltage of 1 V. © VDE VERLAG GMBH.

关键词： Timing circuits

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Step size determination approach for aging simulations in analog ICs 16

Step size determination approach for aging simulations in an...

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作者： Afacan, Engin Department of Electronics Engineering Gebze Technical University Turkey

ISBN: (纸本)9783800755899

Simulation of time-dependent variations is quite complicated since the degradation is a function of time, where the time step directly affects the accuracy and the efficiency of the analysis. Commercial tools use a constant step count during simulations, in which choosing a large step count may degrade the efficiency whereas keeping it small may result in accuracy problems. To overcome this problem, a couple of different adaptive time-step approaches have been proposed in the literature. Nevertheless, they suffer from the initial workload during step count determination or some other accuracy problems. In this study, we present a two-level step count determination approach. At the first level, the step count induced estimation error can be promptly determined via an effective simulation strategy. At the second level, the error is fitted into a saturated power law model;thus, the efficient step count can be determined without any simulation effort. The proposed approach provides a remarkable save in computation time and can be used for all analog circuits without loss of generality. © VDE VERLAG GMBH.

关键词： Efficiency

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Performance assessment of a new low-cost RF sputtered Schottky diode based on a-Si/Ti structure 16

Performance assessment of a new low-cost RF sputtered Schott...

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作者： Ferhati, H. Djeffal, F. Bendjerad, A. Benhaya, A. Department of Electronics University of Batna 2 Algeria

ISBN: (纸本)9783800755899

In this paper, a new efficient and low-cost Schottky Diode (SD) based on a-Si/Ti structure was elaborated using RF magnetron sputtering technique. An exhaustive investigation of structural and electrical properties was performed, where the sputtered device was characterized using X-ray diffraction (XRD) and Keithley (4200-SCS) to measure the current-voltage characteristics. Moreover, a comprehensive study regarding the impact of the Ti layers on the device characteristics is carried out. It was demonstrated that implementing Ti intermediate layers could induce depletion regions at the interfaces, leading to significantly enlarged voltage barrier height. Furthermore, the elaborated SD exhibits a rectification behavior providing an appropriate current with a favorable ideality factor. This is mainly due to the reduced series resistance of the multilayer structure as confirmed by electrical analysis. Therefore, the proposed SD structure based on Ti intermediate layers provides improved performance and can open a new route for the fabrication of promising alternative devices for microelectronic and sensing applications. © VDE VERLAG GMBH.

关键词： Current voltage characteristics

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Connecting energy storages from tool independent, signal-flow oriented FMUs 16

Connecting energy storages from tool independent, signal-flo...

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作者： Ehlert, Meik Michael, Jan Henke, Christian Trächtler, Ansgar Kalla, Matthias Bagaber, Bakr Ponick, Bernd Mertens, Axel Scientific Automation Fraunhofer Institute for Mechatronic Systems Design IEM Paderborn Germany Heinz-Nixdorf-Institute University of Paderborn Paderborn Germany Institute for Drive Systems and Power Electronics Leibniz Universität Hannover Hannover Germany

ISBN: (纸本)9783800755899

In cross-domain system simulation, models from a wide variety of tools are used. The FMI standard provides the possibility to connect these models as Functional Mockup Units. These so called FMUs have signal-flow oriented interfaces to each other. The interfaces can often be inconsistent due to missing knowledge of what kinds of energy storage are present in each model. The inconsistency leads to false simulation results. This article therefore presents design guidelines according to how energy storages can be distributed to different models of the electric drive technology. The goal here is to ensure correct numerical simulations. To validate these guidelines, a drive system is built from several FMUs and is compared against a topology-oriented reference. © VDE VERLAG GMBH.

关键词： Energy storage

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Run-time adaptive hardware accelerator for convolutional neural networks 16

Run-time adaptive hardware accelerator for convolutional neu...

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作者： Sestito, Cristian Spagnolo, Fanny Corsonello, Pasquale Perri, Stefania Department of Informatics Modeling Electronics and System Engineering University of Calabria Arcavacata di Rende Italy Department of Mechanical Energy and Management Engineering University of Calabria Arcavacata di Rende Italy

ISBN: (纸本)9783800755899

State-of-the-art Convolutional Neural Networks are characterized by heterogeneous convolutional layers to proper balance accuracy and computational complexity. Run-time adaptive convolution architectures able to process feature maps with kernels of various sizes and strides are highly desirable to achieve a favorable speed/power dissipation balance. This paper presents the design of an adaptive architecture able to manage efficiently convolutional layers with different running parameters. In order to guarantee high resources utilization for all the supported kernel sizes and strides, in contrast with existing competitors, the proposed design combines non-uniform basic blocks differently customized from each other. As a further nice characteristic, the hardware architecture here presented efficiently manages both odd and even kernel sizes, useful in models also requiring transposed convolutional layers. When accommodated within a Xilinx XC7Z045 FPGA SoC device, the proposed engine reaches a peak throughput of 217.2 GOPS and dissipates about 2.75 W at the 150 MHz clock frequency. © VDE VERLAG GMBH.

关键词： System-on-chip

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Cryogenic RF transimpedance amplifier in 22 nm SOI-CMOS for control of a qubit 16

Cryogenic RF transimpedance amplifier in 22 nm SOI-CMOS for ...

引用

作者： Heinen, Ricardo Nielinger, Dennis Grewing, Christian Wunderlich, Ralf Heinen, Stefan Central Institute of Engineering Electronics and Analytics Electronic Systems Forschungszentrum Jülich GmbH Jülich Germany Integrated Analog Circuits and RF Systems RWTH Aachen University Aachen Germany

ISBN: (纸本)9783800755899

The design and simulation of a cryogenic RF transimpedance amplifier (TIA) for signals around 20 GHz with millivolt amplitudes is presented in this paper. The TIA is part of an IC with a modulator system, where its primary application is to drive a semiconductor based spin qubit at temperatures around 100 mK. A 22 nm FDSOI CMOS technology is used for the circuit development. In post-layout simulations the TIA showed transimpedance magnitudes over 40 dB? and bandwidths larger than 1 GHz while dissipating less than 170 µW. Tuning options for the operating point and the frequency behavior where implemented to ensure functionality at cryogenic temperatures. The TIA performance allows to flip chip bond the modulator system in close vicinity to the qubit inside a dilution refrigerator. This setup can verify if the concept is feasible to upscale qubit numbers. © VDE VERLAG GMBH.

关键词： CMOS integrated circuits

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Germanium–InGaZnO heterostructured thin-film phototransistor with high IR photoresponse 16

Germanium–InGaZnO heterostructured thin-film phototransisto...

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作者： Ferhati, H. Djeffal, F. Bendjerad, A. Department of Electronics University of Batna 2 Algeria

ISBN: (纸本)9783800755899

In this paper, the role of introducing Germanium (Ge)/IGZO heterostructure in enhancing the Infrared (IR) photodetection properties of thin-film phototransistor (Photo-TFT) is presented. Numerical models for the investigated device are developed using ATLAS device simulator. The influence of Ge photosensitive layer thickness on the sensor IR photoresponse is carried out. It is revealed that the optimized IR Photo-TFT based on p-Ge/IGZO heterojunction can offer improved IR responsivity of 4.1×102 A/W, and over 106 of sensitivity. These improvements are attributed to the role of the introduced p-Ge/IGZO heterostructure in promoting IR photodetection ability and improved separation and transfer mechanisms of photo-exited electron/hole pairs. The photosensor is then implemented in an optical inverter gate circuit in order to assess its switching capabilities. It is found that the proposed phototransistor shows an improved optical gain thus indicating its excellent performance. Therefore, providing high IR responsivity and low dark noise effects, the optimized Ge/IGZO IR Photo-TFT can be a potential alternative photosensor for designing optoelectronic systems with high-performance and ultralow power consumption. © VDE VERLAG GMBH.

关键词： Heterojunctions

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Design and analysis of a leading one detector-based approximate multiplier on FPGA 16

Design and analysis of a leading one detector-based approxim...

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作者： Scarfone, Salvatore Frustaci, Fabio Perri, Stefania Department of Informatics Modeling Electronics and System Engineering University of Calabria Arcavacata di Rende Italy Department of Mechanical Energy and Management Engineering University of Calabria Arcavacata di Rende Italy

ISBN: (纸本)9783800755899

In the context of error-tolerant applications, several approximate multipliers have been proposed to trade the energy consumption with the result accuracy. Unlikely, most of them are conceived for Application Specific Integrated Circuits and they can not be implemented on Field Programmable Gate Arrays due to their unique hardware structure. Among the others, the Leading One Detector-based approximate multipliers have attracted a lot of interest due to their efficiency. Nevertheless, a complete characterization of this kind of multipliers on Field Programmable Gate Arrays is still missing. This paper presents a thorough analysis of the approximate multiplier known as Dynamic Range Unbiased Multiplier when implemented on Field Programmable Gate Arrays, and it provides useful design guidelines to get the optimum energy-quality trade-off. Moreover, a simple approximation strategy is proposed to further increase the multiplier efficiency, leading to an energy reduction of up to 34% and a quality increase of up to 43% with respect to the conventional structure. Finally, the possibility of enhancing the referred approximate multiplier with a dynamically tuning of the energy-quality trade-off is analysed. © VDE VERLAG GMBH.

关键词： Field programmable gate arrays (FPGA)

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